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A project log for Clockwork germanium

A retro version of Yet Another (Discrete) Clock, with vintage parts

Yann Guidon / YGDESYann Guidon / YGDES 02/03/2020 at 02:160 Comments

@jaromir.sukuba  sent more more vintage germanium yummies and the cogs and wheels in my head resumed spinning again !

In the log From MUX to Latch, I started investigating other topologies for flip-flops and came up with a cell that was interesting but I wondered if it was optimal. After all the transistors have crawled upon the Earth for something like an eternity now and I've seen many circuits explored in the history, in this project...

The 2-transistor system has been extensively covered by this page and has always been lacking in a way or another. Slow, too many passive parts, tricky to setup... I want something with the fewest parts possible, stable, no capacitor and able to run fast. Even with lousy Ge trannies.

I was still not satisfied with the complex circuit I devised. The transistor count was ok but there are too many diodes for my taste. However the design of this flip-flop gave me more insights into what was good and what was to be avoided.

So I restarted back to the basics and used Falstad's online interactive simulator to build a cell from the basic principles ! And the result is quite unexpected...

It's really very basic ! All the resistors have the same value ! And I have avoided diodes ! You can run the sim with this code :

$ 1 0.000005 2.3728258192205156 60 5 43
g 128 352 128 384 0
g 336 352 336 384 0
t 304 336 336 336 0 1 0.5879810154813296 0.6224917671893107 200
t 160 336 128 336 0 1 -0.5879810154813296 0.03451075170798105 200
r 128 256 128 192 0 1000
r 336 256 336 192 0 1000
w 256 336 208 288 0
w 208 336 256 288 0
w 256 288 336 288 3
w 336 320 336 288 0
w 208 288 128 288 3
w 128 256 128 288 0
w 128 288 128 320 0
w 128 176 240 176 0
R 240 80 240 32 0 0 40 2 0 0 0.5
w 160 336 208 336 0
w 256 336 304 336 0
w 240 112 240 176 1
w 48 288 16 288 3
w 240 176 336 176 0
r 96 96 176 96 0 1000
r 48 288 128 288 0 1000
L 16 288 -16 288 0 1 false 0.63 0
L 96 96 64 96 0 1 false 2 0
w 336 288 336 256 0
w 208 96 176 96 3
t 208 96 240 96 0 1 -0.01041339040851752 0.6145396107402716 200
w 128 176 128 192 0
w 336 192 336 176 0

You can find the classic flip-flop with its two interlocked transistors, you can't make it more simple. I have chosen the version with only 2 resistors on the collectors, not the bases.

Then there is an emitter-follower that powers the flip-flop. The clock must go all the way up to the +Vcc rail but the driving current is nicely low, and decreases as the beta of the transistor increases. So a single PNP transistor could drive the main clock of a group. There is a 0.6V drop but it doesn't matter much. Swap it for a PNP if you prefer. It's interesting however because it insulates the pair of switching transistors from the supply, we'll see later why. The emitter follower can also be used to tune the supply voltage and current and more of these can be chained together.

So where does the data come from ? That's the whole trick in fact and it's not obvious...  The principle/idea is :

The solution I have found is apparently a simple resistor...


I still have some cases where the FF initialises with both transistors passing and I can't see why. Falstad can show some weird transient behaviours but something else is happening and I suppose SPICE would solve or resolve these patterns.

The resistor liaison seems to work almost well but relies on a very low input impedance behind the resistor, which might not be available, particularly in this circuit where I try to reduce the current as much as possible (because if it works, this circuit would be replicated tens of times !)

So I'm struggling to get a low impedance output and avoid forbidden states in the FF.

Anyway, 3 transistors and 3 resistors is a very promising circuit for a latch and I'll try to make it a full DFF !


The "bad starts" seem to be solved by taking the data input lower than the emitter of the nearby emitter. I don't want to add more rails and other crazy stuff but... I had the idea to "shift" the emitters with a resistor (it's also called "degeneration") and it seems to do wonders. The result has many advantages !

You'll notice that the LOW input level is 400mV and the HIGH input level is 900mV, inside the margin of the output swing (360mV-966mV).

This adds only 2 small resistors and we have the following ratios :

Only real implementation will tell if the speed it enough for my projects...

Here is the simulation of this new latch with Falstad :

And the source code :

$ 1 0.000005 2.3728258192205156 60 5 43
g 128 448 128 480 0
g 336 448 336 480 0
t 304 336 336 336 0 1 -0.5726792194301711 0.393378078449324 200
t 160 336 128 336 0 1 0.5726792194301711 0.6111078340910289 200
r 128 256 128 192 0 1000
r 336 256 336 192 0 1000
w 256 336 208 288 0
w 208 336 256 288 0
w 256 288 336 288 3
w 336 320 336 288 0
w 208 288 128 288 3
w 128 256 128 288 0
w 128 288 128 320 0
w 128 176 240 176 2
R 240 80 240 32 0 0 40 2 0 0 0.5
w 160 336 208 336 0
w 256 336 304 336 0
w 240 112 240 176 1
w 48 288 16 288 3
w 240 176 336 176 0
r 96 96 176 96 0 1000
r 48 288 128 288 0 2000
L 16 288 -16 288 0 0 false 0.9 0.4
L 96 96 64 96 0 1 false 2 0
w 336 288 336 256 0
w 208 96 176 96 3
t 208 96 240 96 0 1 -0.0070514786969611 0.6044560065624918 200
w 128 176 128 192 0
w 336 192 336 176 0
r 336 448 336 384 0 250
r 128 448 128 384 0 250
w 128 352 128 384 3
w 336 352 336 384 3

 From there on, it should be easy to create a shift register...


Well, it was not as easy as I thought ! And Falstad gives me a lot of troubles with weird simulations that seem random and give results that vary from one run to the other. I had to add capacitors to stabilise some things...

The good sides are : it uses fewer parts and draws less current (about 3mA with these parameters). Only 2 diodes have been added for the liaison, which is a pretty neat and cheap compromise.

Here is thesource code for the sim :

$ 1 0.000005 0.13386567243530942 58 5 43
g 128 448 128 480 0
g 336 464 336 480 0
t 304 336 336 336 0 1 -0.5841634814225252 0.4903224664076705 50
t 160 336 128 336 0 1 0.5841634814225252 0.6209564153103788 50
r 128 256 128 192 0 1000
r 336 256 336 192 0 1000
w 256 336 208 288 0
w 208 336 256 288 0
w 256 288 336 288 3
w 336 320 336 288 0
w 128 256 128 288 0
w 128 288 128 320 0
w 128 176 240 176 2
R 240 32 240 0 0 0 40 3 0 0 0.5
w 160 336 208 336 0
w 256 336 304 336 0
w 240 128 240 176 1
w 48 288 16 288 3
w 240 176 336 176 0
r 96 112 176 112 0 1000
r 48 288 128 288 0 2000
L 16 288 -16 288 0 0 false 1.2 0
L 96 112 64 112 0 1 false 3 0
w 336 288 336 272 0
w 208 112 176 112 3
t 208 112 240 112 0 1 -0.01565201462221122 0.6250797824248919 200
w 128 176 128 192 0
w 336 192 336 176 0
r 336 448 336 384 0 220
r 128 448 128 384 0 220
w 128 352 128 384 3
w 736 352 736 384 3
w 528 352 528 384 3
r 528 448 528 384 0 220
r 736 448 736 384 0 220
w 736 192 736 176 0
w 528 176 528 192 0
w 608 112 528 112 3
w 736 288 736 256 0
w 656 176 736 176 0
w 304 80 96 80 3
w 640 128 640 176 1
w 656 336 704 336 0
w 528 176 608 176 2
w 528 288 528 320 0
w 528 256 528 288 0
w 608 288 528 288 3
w 736 320 736 288 0
w 656 288 736 288 3
w 608 336 656 288 0
w 656 336 608 288 0
r 736 256 736 192 0 1000
r 528 256 528 192 0 1000
t 560 336 528 336 0 1 0.5612474813757181 0.5967515964862364 50
t 704 336 736 336 0 1 -0.5612474813757181 0.21207598906918554 50
g 736 448 736 480 0
g 528 448 528 480 0
w 240 32 240 48 1
w 240 48 240 96 0
w 240 48 288 48 0
w 640 48 640 96 0
w 96 80 96 112 0
t 608 112 640 112 0 1 -2.3418004906459884 0.1654996677481867 200
r 304 80 384 80 0 100000
w 416 48 528 48 0
w 416 96 416 112 0
t 384 80 416 80 0 -1 2.3418004804459738 -1.0000014594169215e-8 100
w 416 48 416 64 0
w 528 48 640 48 0
r 416 112 528 112 0 1000
w 336 384 336 352 2
w 336 464 336 448 1
w 208 288 128 288 3
w 336 256 336 272 0
w 496 288 528 288 0
w 288 48 416 48 0
w 560 336 608 336 0
w 464 288 496 288 1
d 400 304 464 304 2 1N4148
d 400 256 464 288 2 1N4148
w 464 304 512 304 1
w 512 304 576 304 0
w 656 256 656 288 0
w 400 256 240 256 0
w 240 256 208 288 0
w 640 176 656 176 0
w 640 176 608 176 0
w 608 336 576 304 0
c 656 256 656 176 0 1e-9 0.28062371048784684
c 608 288 608 176 0 1e-9 -0.28062377088787127
w 336 288 400 304 0
x 558 210 668 213 4 14 1nf\sfor\ssim\sonly
38 22 2 0 3 CLK\slow
38 22 1 0 3 Clk\sHigh
38 21 2 0 3 Din\sLow
38 21 1 0 3 Din\sHigh

 And a little video...

It is obviously still flawed but we're almost getting there ;-)

...

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