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Data RAM parity

A project log for AMBAP: A Modest Bitslice Architecture Proposal

Trying to unify and simplify a minimal architecture for various implementation technologies...

yann-guidon-ygdesYann Guidon / YGDES 11/21/2016 at 15:534 Comments

In Memory arrays for relay toy^Wcomputer I suggested that parity would be an important feature. It will help evaluate the actual data retention time of the whole array, and detect run-time storage errors.

Parity is just a XOR of all the bits, stored in an additional bit/plane of the memory array. To do this, the usual method is to make a tree of XOR2 gates. Given the propagation time of the relays, the tree would need 4 or 5 "relay times" (15 to 20ms ?) and slow the whole computer down.

Do you remember the DPDT circuit in the log Dual-voltage power supply? Well, it's not only a solution to the carry chain but also to the XOR tree. On top of that, since it's a O(1) kind of circuit, the XOR gate can be located on the bitplane: on the globule or the RAM board.

There will be one more RAM board than globule slice so the read sensor, the write buffer, the parity and such should be located on the RAM board.

Furthermore, the parity must be computed during read and write cycles, so 2 circuits are needed. That's 2×2×16=64 relays overall, or 2 boxes. But there could be a trick if speed is not critical, as the parity can be looped back from the sense relay :-) I should sketch it to be sure...

Discussions

Ted Yapo wrote 11/21/2016 at 18:14 point

What do you do if you detect a parity error?  Without a higher-level ECC controller and some more check-bits, you can't correct anything.  But, will you halt the machine?

I see how just flagging errors would be useful for evaluating the required refresh time, as you mention.  Knowing if your refresh task is getting enough cycles (assuming a software refresh) is another good one.

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Yann Guidon / YGDES wrote 11/21/2016 at 18:18 point

That's more or less the idea : be sure that there is no GIGO going on.

If I have a refresh cycle every minute and the system can hold data for 3 minutes, I'm fine.

I can also analyse which lines are the most "forgetful" and spot the weakest caps.

So no, ECC would be overkill, for such a toy, I'm not piloting a spacecraft (as did the Russians) :-D

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Ted Yapo wrote 11/21/2016 at 18:32 point

I had a lab-mate in grad school who couldn't get a large piece of someone else's code to work correctly - he spent a lot of time trying to debug this code before he determined that there was a bad DIMM in his PC.  Memtest86 found it right away.

Don't underestimate the convenience of reliable RAM...imagine if notes and sketches sometimes mysteriously changed in your notebook.  What a mess...

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Yann Guidon / YGDES wrote 11/21/2016 at 18:38 point

I understand it well, and that's why I invest relays in the parity checks :-)

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