Just a quick post of this week's changes:
The CPU's interrupt module is implemented and (should be) working. My plan is to replace it at some point with a more advanced system, but for now the simple version is fine.
I've started writing the assembly specification document. It defines the format for epRISC assembly files, as well as assembler directives and the full instruction set.
I've also started defining the sysX (SYStem eXpansion) protocol. It's essentially just Quad SPI with wider data buses and multiplexed chip select lines. I'm using it to connect the CPU to the I/O controllers on the auxiliary FPGA.
The epRISC assembler, spasm, is now in the GitHub repository. I haven't changed it at all yet, so it still targets the v4 ISA.