Almost Working

Updated and tested the Software Data Protection version on the FRAM programmer.

I had set my self a trap! "A14" is not set using SetAddr(), It has its own routine. But it is working now. I have uploaded the code.

Endless Loop

I also wrote a Control Card simulation so I could test the bus. Surprisingly the CPU is mostly working before going into an endless loop.

It fails when I try to change the ROM Page. It should wait until a jump before changing the Page but it changes the Page immediately.

It seems as if the LOAD signal (which signals the PC to jump on the next clock) is glitched.

Using the logic analyzer I did (once) get it to show glitches every write machine cycle.

How to fix?

Cross-talk on the CLR Signal

I am getting about 5 clock cycles on the CLR signal as the Reset triggers reset schmitt trigger. It does not appear to affect (but there is some evidence that it does!) the control circuit. It could be internal cross-talk (as the clock and reset circuity share the same chip) or external cross-talk because the components are close together.

I am thinking of adding a 47 pF capacitor to the input gate of the reset logic.

Next time I will use a 74HC14 rather than build my own Schmitt trigger.

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The capacitors did not work.

Redesigned the clock and reset circuity.

Redesigned the load signal to avoid the glitch areas between the machine cycles.

Redesigned the boards and sent them off to be made.

Bugger no sooner than I sent the order off I found an error.

Oh well, I will sent the updated board tomorrow.

I am getting close to working!

AlanX