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Connecting I/O

A project log for FPGA Bootcamp #2

Take the next step with FPGAs: Sequential logic!

Al WilliamsAl Williams 06/23/2018 at 03:040 Comments

In the last bootcamp and this one, we've connected to things like LEDs and clocks. But how does Verilog know where those things are? The answer is right now, it doesn't. If you don't do anything, the tools will assign the pins anywhere it wants and since we already have a PCB with clocks on some pin and LEDs on some pins, that just won't do.

The Verilog right now isn't being configured to go to the chip. So whatever names we decide on match up in the design and the testbench and that's fine. But in the next bootcamp that won't be good.

Each tool has a slightly different way of handling things, and we'll talk about the tool we will use in the next bootcamp. But, in general, all tools will have some way to create constraints. Most tools can take lots of different kinds of constraints and one of them can be used to define I/O mappings.

What's a constraint? Remember once your Verilog is processed, the tools will map what you have asked for into blocks the FPGA has and then figure out how to connect them together. A constraint tells the system something it must do during that process. Of interest to us now is to say "Hey, the signal called clk needs to be in an I/O buffer that connects to pin X." The router will be sure that happens as it juggles around trying to find the best way to lay out the design.

There are other kinds of constraints. For example, you might tell the system that the timing between two points has to be no more than 20 nS, for example. Or that two blocks need to be put next to each other. That's pretty rare, but sometimes you need it. In particular, you will usually provide a clock constraint that will tell the tool the clock frequency you intend to use and it will tell you if you have delays that would cause problems. This is known as "not meeting timing" and we'll talk about it a lot in a future bootcamp.

How do you set these constraints? That depends on the tools. Common tools will let you put special comments in the Verilog file or provide a text file with constraints in it. Some tools will have a GUI that can build or edit that text file, too -- some will have a few choices of GUIs.

Again, we'll look at exactly how this works for the IceStick in the next bootcamp, but I wanted you to be aware of the necessity and importance of this no matter which tools you are using.

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