The data width of the CPU is 8 bits.
The CPU will now have four address registers (instead of the single HL register pair ).
The address registers are 20 bits wide. Regular instructions will operate on the lowest 16 bits, and there will be special instructions to fill the upper 4 bits of each register.
PC program counter
WP workspace pointer
X index register
Y index register
There will be two 8-bit accumulator registers, coupled to the new ALU. They can, together,
contain a 16 bit value.
Hopefully, the microcode can stay 8 bits wide.
For the moment, this is the idea for the micro-instructions:
00AA DDDD load accumulator 8bit, addr register AA with displ. DDDD 01AA DDDD store accumulator 8bit, addr register AA with displ. DDDD 10AA DDDD add to accumulator, addr register AA with displ. DDDD 1100 FFFF set ALU function FFFF (instead of the default ADD) 1101 AA00 16-bit accumulator to addr. register AA (bits 0-15) 1101 AA01 16-bit accumulator to addr. register AA (bits 16-19) 1101 AA10 16-bit accumulator to addr. register AA if true (bits 0-15) 1101 AA11 16-bit accumulator to addr. register AA if false (bits 0-15) 1110 FFFF reserved for I/O 1111 FFFF microcode jump
[edit: a new version of the microcode is found here]