Opcode handling

A project log for Kobold - retro TTL computer

A computer with 20 address bits, 16 bit instructions, video display, from just a few TTL and memory chips. Aiming for PDP11 instruction set.

roelhroelh 04/15/2019 at 17:173 Comments

The Kobold is advertised to handle 16 bit instructions, but everything is 8 bit. Even the microcode is only 8 bit wide. How does it work ?

[ What you need to know for the examples: The program counter is in register R7 (as on the PDP11), and is copied into address register PC when needed. The lowest bit of the PC is always 0.]


As example, take an instruction that adds (X+6) to register R4:

 add (X+6),R4 

The instruction is split into two parts, that operate almost independent of each other:

The first byte of the instruction is fetched from (PC) into the micro-program counter. From here, the micro-instructions determine the operation:

This instruction byte tells to add R4 (16 bits) to the accumulator and store the result back to R4:

The next section of the microcode will increment the PC and start the next instruction:

EXAMPLE: 8 bit immediate load

There are also instructions that have a single opcode byte, followed by an 8-bit immediate operand or z-page location. Branch instructions are  an example of this.

As example, load register R3 with value 0x80:

mov #0x80,R3

Finally, the pc is incremented and the next instruction is fetched, as in the previous example.


Yann Guidon / YGDES wrote 04/16/2019 at 03:13 point

It's funny how we were used to CISC 40 years ago and now I cringe at the evocation of this idea :-D

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roelh wrote 04/16/2019 at 11:30 point

I'm sorry Yann, the minimum parts requirement drove Kobold in the arms of CISC....

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Yann Guidon / YGDES wrote 04/16/2019 at 16:20 point

I notice that the CISC way can require more gates than RISC because you need some scheduling here, buffers there, some fix for a corner case...

That's why I prefer to focus on the core datapath (speed/efficiency/simplicity), then I build decoders out/around :-)

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