A minimal DIY 8-bit CPU made with TTL chips, to perform native brainfu*k language, extended to use three sequential access tapes.

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How make a new cpu without memory address access, using only sequential access, for code, data and input/output ?

I want to learn about how old cpus are made by inside and understand about signals, gates, latches, pipelines, TTLs etc.

Jelly runs a minimal language, brainfunk*, a superset of brainfuck, a minimal Turing-complete programming language, which works with sequential access to two infinite tapes, just moving forwards or backwards.

But Jelly includes a third tape for I/O and few new commands to self.



I'm a passionate hobbist with interest in digital electronics,
This project is about practicing and learning.
This is a personal project, with entertaining and educational objectives.


** This is still a brainstorm, I'm a newbie in TTL circuits **

What is it ?

Jelly is a concept, a alternative computer with a diferent paradigm, not for performance but for design.

Jelly uses three ideal tapes, first for code (aka BOB),  second for data (aka ONE), third for input/output (aka TWO).

Any memory device could emulate a tape, and the i/o tape could be just as a memory mapped i/o ports, like in many microcontrolers.

About op-codes

At first, lets resume the 16 opcodes for Jelly brainfunk;

descriptioncode set                                  
jellyno operation
1=swap tapes
jellyswaps tapes, just for moves
2>forward tape one position
brainfu*kdata or i/o tape, vide swap
3<backward tape one position
brainfu*kdata or i/o tape, vide swap
4+increment byte at tape position
brainfu*konly for data tape
5-decrement byte at tape position
brainfu*konly for data tape
6.output a byte at tape position
brainfu*kfrom data tape into i/o tape
7,input a byte to tape position
brainfu*kfrom i/o tape into data tape
8[test if byte at data tape is zero, and forward code tape to matched ]brainfu*kallow nested loops
9]test if byte at data tape is not zero, and backward code tape to matched [
brainfu*kallow nested loops
10~unary negation
reservedjellystill does noop
separator for code and datajellyend of program
jellyrestart the cpu
14$haltjellyhalt the cpu
jellyend of file


minimal Jelly, version zero.six

dig - 83.04 kB - 09/15/2022 at 16:02



control logic steps for halt and flag signals

Portable Network Graphics (PNG) - 155.63 kB - 09/12/2022 at 14:24



full bare bones circuit for Jelly

dig - 91.02 kB - 09/12/2022 at 14:24



control logic steps for halt and flag signals

dig - 33.39 kB - 09/12/2022 at 14:24



toggle logic for loops [ and ] using bob-one-rd-wr-zero signals to instant change eeprom page

dig - 9.26 kB - 08/30/2022 at 15:08


View all 7 files

  • 4 × 74hc574 8 x D-register, with 3-state, clock, output enable
  • 5 × at28c16 2k * 8 Memory ICs / EEPROMs
  • 1 × 74hc193 4-bit counter
  • 4 × 74hc00 4 dual NANDs
  • 4 × 74hc32 4 dual OR

View all 11 components

  • minimal Jelly

    Alvaro Barcellos09/15/2022 at 16:28 0 comments

    "Something in the way, she is moving"

    Looking at circuits done in Digital application,  Jelly could be more simple.

    There are one circuit with a eeprom to control tape devices, and two  circuits between a buffer (74hc574) to a eeprom (at28c16).

    For the tape circuit, just need control the OE of eeprom.

    For the code circuit, just need control CE of buffer.

    For the math circuit, with feedback, need control CE of buffer and OE of eeprom.

    All others signal of CE, OE, inside closed circuits, goes enabled forever.

    These simplify control signals to CE1, OE2, CE3, OE4, plus M1, M2 for 4 operations math, plus A8 and A9 for 4 pages extended.

    (These changes are in file jelly-six.dig).

    As some combinations of signals for tape devices are also used to setup flags as swap, move and halt, need some complementary logics.

    (These changes are in file jelly-six-halt.dig).

    "Something in the way, she moves"

  • loops without jumps

    Alvaro Barcellos09/09/2022 at 13:02 0 comments

    Jelly must have some external logic to complement FSM eeproms.

    The way found to simulate an "IF" or "ELSE" was to change the "page", depending on external conditions.

    Circuits define "check and clear" logic. For bob, one, two signals, when two are active they are used to validate the conditions. For signals fw, bk, rd, wr, which cannot be active simultaneously.

    The one and two signals are used to activate the swap signal, which works like a toggle switch that inverts the selection between one and two.

    The bob and one signals are used to activate the move signal, which works like a toggle switch that inverts the selection between move forward or backward. This is needed to simplify the loop logic.

    The bob and two signals are used with the zero signal to select "page one" by activating a  toggle switch for address a08. In the "page one" commands just executes a next opcode, else [ and ], that increase or decrease a counter.

    The pseudo code for processing [ and ] loops in "page one" :

    for ( ; ; ) {
          if (c==[) cnt++;
          if (c==]) cnt--;
          if (cnt == 0) break;
          c = next();


    the next action is a tape bob sequence of  move and read. move could be forward or backward. the move signal toggles setup direction and both could be coded as a single operation move.

    the logic circuit is showed in file jelly-two-halt.dig

    -- this still a stub ---

    the conditions table of loops [ and ] could be resumed as

    10[zero == NO
    20[zero  == YES
    go page 1
    31[zero == NO
    inc count, next
    41[zero == YES
    inc count, next
    50]zero == NO
    go page 1
    60]zero == YES
    71]zero == NO
    dec count,  prev
    81]zero == YES
    go page 0

  • How make it

    Alvaro Barcellos09/06/2022 at 21:01 0 comments

    Good news.

    Going through lists of TTLs and cpus and diy homebrew projects, I have a good feeling that I'm not doing anything very different than what has already been done for different purposes.

    Using eeproms to save logic by defining FSM to control the signals, aka microcode, is common practice. Use 3-state latchs to isolate shared data bus, ditto. Use counters to synchronize pipeline phases, ditto. Use eeprom to define the results of mathematical operations, ditto.

    I still need to figure out how to process flags, state toggles and other synchronisms.

    All the TTL chip circuits have arrived, so I can start building and testing.

    First, I need to build an eeproms programmer, see eepromgrammer.

    some links for same uses.

    The Mark One computer also have a opcode set very like Jelly one's.

  • Jelly as a HRM

    Alvaro Barcellos08/31/2022 at 16:10 0 comments

    Today, I discover about "Human Resource Machine",  ( by and

    The hrm-cpu is a "human" sequential machine, with restrict set of instructions, very like as Jelly's ones.

    The HRM literal jumps behave as BF loops \[ and \] and  the HRM literal bumps behave as BF  \+ and \-.  Add and Sub are trivial.

    Jelly can process as a 8-bit HRM, using ten or more i/o tape cells as internal storage and few macros.

  • Maths

    Alvaro Barcellos08/25/2022 at 14:48 0 comments

     Jelly have a change in signals for  fake ALU eeprom.

     Now the low byte address is the argument and high byte address is the operation.

     Only unary math are allowed, and using address A08, A09, A10, the operations are:

    high byte (page)
    (00011011 => 00000000)
    (00011011 => 00011100)
    (00011011 => 00011010)
    (00011011 => 00011011)
    (00011011 => 11100100)
    101shift left
    (00011011 => 00110110)
    011shift right
    (00011011 => 00001101)
    (00011011 => 11011000)

    Only clear, increase, decrease and copy are current in Jelly.

    PS. mirror is reverse bit order, as from little endian into big endian and vice-versa.

  • lock signals

    Alvaro Barcellos08/20/2022 at 02:55 0 comments

    Most of opcodes of brainfunk are simple sequences of simple states, that could be mixed using OR, also  to select and enable  buffers.

    But for  '[' and ']'  need know a result of a test if value is zero and change the behavior from 'execute' to 'search'.

    Jelly does it by using  pages on eeproms, with diferent set of finite states. Simple as turn on a bit, but not.  

    Pages are mapped with high byte of eeprom, (in a at28c16 uses a8-a10 for 8 pages) and some logic must set and unset this bits.

    ------------------------------- paused, will continue

  • golden ratio

    Alvaro Barcellos08/18/2022 at 01:17 0 comments

    Brainfuck is a complete Turing language, (

    For who do not know brainfunk, look at code bellow, see also

    [golden.b -- compute golden ratio
    (c) 2019 Daniel B. Cristofani]
    This program computes the "golden ratio" 
    Because this number is infinitely long, 
    this program doesn't terminate on its own;
    you will have to kill it.

  • tapes and loops

    Alvaro Barcellos08/13/2022 at 23:47 0 comments

    Jelly uses tapes. Sequential tapes and only two types of loops:

    One checks if  data value is zero then moves forward until matched, other checks if  data value is not zero then moves backward until matched.

    All loops must be running by compare the value at tape with [ and ] and increment or decrement a counter, forward or backward a step, until counter is zero.

    As pseudo code shows, both loops only differs at forward and backward move.

    By using a byte as counter, a maximum nested loops is 255.

    how make nested [ and ] ?
    // for [
    do {
        if (*dp == ‘[‘ ) cnt++;
        if (*dp == ‘]’ ) cnt--;
        }while (cnt);
    // for ]
    do {
        if (*dp == ‘]‘ ) cnt++;
        if (*dp == ‘[’ ) cnt--;
        }while (cnt);

  • Minimal concept

    Alvaro Barcellos08/13/2022 at 23:44 0 comments

    Jelly no have counters or ALU, but have excellent memory.

    In Jelly, only one byte value can be accessed a time.

    Then Jelly have now 3 modules:

    1. Code: with one 74hc574, one at28c16, one 74HC193, some TTLs for clock

    2. Data: with two 74hc574, two at28c16

    3. Control: with two 74hc574, two at28c16

    No more.

    the eeprom at28c16 is just 2k x 8 bits, no need more.

    (but need some extra logic chips for flags.)

  • signals layouts

    Alvaro Barcellos08/13/2022 at 23:38 0 comments

    Jelly now have two buses:

    external/internal bus

           block bus      (BOB, ONE, TWO, HLT, RD, WR, BK, FW)

           data bus        (D0, D1, D2, D3, D4, D5, D6, D7)

           extra bus       (VCC, GND, CLK, HLT, R0, R1, R2, R4)

    only internal bus

          code bus       (M0, M1, M2, M3, M4, M5, M6, M7) 

          block code    (CP0, OE0, CP1, OE1, M8, M9, M10, M11)

          block data    (CP2, OE2, CP3, OE3, OP0, OP1, OP2, OP3)


    D0-D7 are data bits, M0-M11 are eeprom address bits,

    HLT main halt, CLK main clock, GND ground and VCC power,

    OP0, OP1, OP2, OP3  select math operation

    R0, R1, R2, R3  reserved for future use

View all 15 project logs

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