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25/09/22 - Extension Board Interface & Abstraction
09/25/2022 at 00:45 • 0 comments---------- more ----------On the outside of the schematic which abstracts the hardware mappings, you refer to the datasheet listed titles for functions of the RP2040, and while in the firmware you would need to address the correct mappings of pin-to-interface, this makes it possible to work with the final pin functions.
At the end of the day, if both two pins (i.e GPIO4 and GPIO10) are used for function A or B, and both _can_ perform A *OR* B, then the order does not matter. Instead, in the parent schematic, all you see is:
And you simply connect the pin for X to the thing that needs X. For example:
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24/09/22 - v3.5.0-A: Layout adjustments & Improvement leads
09/23/2022 at 21:10 • 0 commentsI'm starting to think about changes to make to the design. I don't consider this version to be the next release, it's a subversion and extension of the previous v3.0.0 design.
This log is going to be updated later today, so I'm providing some pictures and will check back in later. Sorry :)
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22/09/22 - Assembly! ...and some mistakes
09/22/2022 at 07:25 • 0 commentsCheck. It. Out!
The first board has been assembled! I placed the buttons on the opposite side (Intentional, and a great demonstration of one of the assembly of the board; Placing the through-hole components on either side has zero effect on functionality. Students always screw that one up.)
---------- more ----------I did however... forget to purchase the USB connectors, the right sized USB termination resistors, and... the fixed LDO regulator. I guess that now explains why the order was $400 cheaper in reality.
The "Correct" (D-pad is on the left) orientation looks like this:
Which is the board my friend put together with me. You can probably spot the exposed via's. That was, I suppose not really my fault, but a problem with the PCB order. The JLC plugin I was using seems to have overwritten my soldermask expansion setting, resulting in the unfortunate complete exposure of every single via.
Assembling the board myself, I was able to get everything on there around the MCU without serious shorts, but it does concern me for the broader student audience. Functionally the board will be fine.Stay tuned for when I fix all my mistakes, for the next iteration of the boards.
Easter egg:
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v3.0.0 is ordered, future changes
09/07/2022 at 22:22 • 0 commentsRevision A of v3 of the board has gone out in an order. Hopefully they arrive soon so that I can post an update and show a working board. In the meantime...
---------- more ----------There were a number of last minute hacks I had to make. I didn't notice this, but the AZ1117-3.3 regulator I had selected originally was pretty unusual in that it placed the output rail on pin 3 instead of thoug the tab (SOT223-tab) and pin 2. Result:
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v3.0.0 - Final Layout, Components & Order
09/06/2022 at 11:24 • 0 commentsThe board is pretty much done for its first release.
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v2.5.0 - Some general design notes, trace layout rework
09/03/2022 at 14:50 • 0 commentsI started from scratch with the routing.
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v2.0.0 - A smaller, cheaper, better thought out attempt
09/03/2022 at 14:35 • 0 comments---------- more ---------- -
v1.0.0 - The first design, that I didn't use
09/03/2022 at 14:17 • 0 commentsThe first version of the board (pictured below) was made to satisfy JLCPCB's tighter standard 4-layer via tolerances. This turned out to be an issue, and there were a few other reasons I moved to later designs.
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