Close
0%
0%

TinyD, 8-bit stereo class D amp from Attiny85

The goal of this project is to create an 8-bit 32khz class d amplifier, using filterless topology, controlled by an Attiny85

Similar projects worth following
The goal of this project is to create an 8-bit 32khz stereo class d amplifier controlled by an Attiny85. I built a similar model back in 2014 based off the ATtiny461. This new version will be ported to the more popular ATtiny85.

I changed the scope of this project due to time constraints. My original intent was to have the class d output 0% pwm at rest, but it will now output 50% pwm at rest. Perhaps I will revisit this project in the future to address.

The audio inpus (L+R) are fed through a 10uF decoupling capacitor to a voltage divider that provides a bias of approximately .55v. The 10uF cap and 560 ohm resistor act as a high pass filter, with the cutoff frequency at ~28Hz. If I had to do it again, I'd put a smaller value capacitor on there to raise the cutoff frequency since the amp is prone to distortion on the lower frequencies.

The signals are then fed into the attiny85 via pins ADC1 &ADC3. The ADC is setup using a 1.1v voltage reference since line inputs are typically ~1v. Also, the ADC prescaler is set at 16, giving the ADC clock a frequency of 500m

kHz. Anything over 200khz is recommended to use only 8-bit accuracy, as 10-bit accuracy requires more time. The ADC is started, using the ISR to change the channel that is read, switching from 1 to 3. One value is stored as OCR1A, the other as OCR1B.

Timer1 is setup using PWM1A and PWM1B, set to turn on the corresponding pins when a compare match with OCR1A and OCR1B is made, and then clearing them when the timer reaches 0. Once setup, this is done in hardware, which aids in the reliability of the amp. This causes the pwm frequency to be proportional to the input(s) amplitude.

I did not use a filter on the speakers, but it is highly recommended to filter out the 50% duty cycle 32.5kHz carrier signal.

main.cpp

Executable c++ file

cpp - 2.35 kB - 01/02/2017 at 02:26

Download

TinyD_Rev4.hex

.hex file compiled from atmel studio 7.0

hex - 459.00 bytes - 01/02/2017 at 02:26

Download

tiny85_classd.sch

Eagle 7 schematic file

sch - 650.96 kB - 01/02/2017 at 02:01

See BOM Download

tiny85_classd.brd

Eagle 7 board file

brd - 43.71 kB - 01/02/2017 at 02:01

Download

tiny85_classd.bot.etch.ngc

LinuxCNC etch g-code

ngc - 26.04 kB - 01/02/2017 at 02:01

Download

tiny85_classd.bot.drill.ngc

LinuxCNC drill g-code

ngc - 2.40 kB - 01/02/2017 at 02:01

Download

tiny85_classd.bot.mill.ngc

LinuxCNC mill g-code (cuts the outline of the board)

ngc - 465.00 bytes - 01/02/2017 at 02:01

Download

schematic20.png

The most recent schematic

Portable Network Graphics (PNG) - 17.24 kB - 01/02/2017 at 02:00

Preview Download

board20.png

The most recent board image

Portable Network Graphics (PNG) - 10.88 kB - 01/02/2017 at 02:00

Preview Download

View all 9 files

  • 1 × ATtiny85 Microprocessors, Microcontrollers, DSPs / ARM, RISC-Based Microcontrollers
  • 1 × .1uF capacitors
  • 2 × 10uF capacitors
  • 1 × 10k resistor
  • 2 × 4.7k resistors
  • 1 × 3mm LED w/ built in resistor
  • 1 × 1/8" audio jack
  • 2 × 1x6 female pin header
  • 1 × 1x2 pin header with jumper
  • 1 × H-bridge motor driver based on L298N

View all 12 components

  • Video of operation

    George Gardner01/02/2017 at 13:13 0 comments

  • About complete

    George Gardner01/02/2017 at 01:59 0 comments

    I'm just about completed with the project. I was able to make it stereo while keeping the 32khz sampling rate @ 8 bits.

  • Had to scale back the project

    George Gardner01/01/2017 at 15:20 0 comments

    Unfortunately, I do not have enough time to complete the project by the Jan 5 < 1k challenge date so I must change the scope of the project so that I can complete.

    The intent of this project was to create a Class D amp from an ATtiny85 using FILTERLESS (0% PWM at rest) topology; however, I'm having trouble with distortion at the zero cross, and I don't have enough time to diagnose and fix this issue.

    I will be changing the scope of the project to use standard Class D methods (50% @ rest) which will require a filter on the output end. :(

  • The dreaded zero cross

    George Gardner12/31/2016 at 12:22 0 comments

    Well, I've run into the same issues I was having with the project from 2014. I don't know if it's related to switching times, but when the PWM crosses from positive to negative, there seems to be a good deal of distortion, and the audio quality suffers at lower volumes.

  • Rev 2

    George Gardner12/30/2016 at 18:54 0 comments

    Made some rookie mistakes on the design of the first board. I could have added a rats nest to the first PCB, but decided to run off another one. Programming starts tomorrow!

View all 5 project logs

Enjoy this project?

Share

Discussions

Elliot Williams wrote 01/23/2017 at 09:41 point

Neat project, and I hope you finish up even without deadline pressure. :)   

  Are you sure? yes | no

K.C. Lee wrote 01/07/2017 at 21:26 point

>the ADC prescaler is set at 16, giving the ADC clock a frequency of 500mhz

500kHz?  Also note proper capitalization for units does not follow English rules.

  Are you sure? yes | no

George Gardner wrote 01/11/2017 at 20:49 point

Thanks. 

  Are you sure? yes | no

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates