• Reverse-Engineering Diagrams

    Keri Szafir • 08/28/2023 at 12:12 • 0 comments

    First, it was tracing the connections between chips on the control board, resulting in the Diagram of Discombobulation:

    ...and then, recombobulating the aforementioned diagram into something easier to understand and trace.


    The system is built around a KR1820VE1A microcontroller, an equivalent of the antiquated COP402. Its "defining" feature is lack of built-in ROM; it uses an external chip instead (KR573RF5, equiv. 27C16 with 25V programming voltage, marked "P64"), and can address up to a kilobyte of program memory. A clever trick called bank switching was used in the Lell PSR design, allowing the MCU to use not one, but two kilobytes of memory for firmware storage - with a possibility of extending that by another ROM chip (unpopulated and possibly storing the MIDI functionality). This is done by setting an additional bit on the address port of 27C16.

    A single I/O port (IP0...7 and P8, P9) is used both for addressing the memory and reading the data from it; the direction is dictated by high or low state on pin 33 (AD/~DATA). There is a latch (KR1533IR23, equiv. 74ALS374) which traps the data and outputs it to the MCU's IP0...7 port when it is in the data input mode.

    Now, on to the synchronization and clock port, D0...3. It's a 4-bit output feeding into a pair of K561TM2 double D latches which trap the data making its state stable for an entire master clock cycle (running at 25kHz; the MCU's clock input runs at 4MHz from an external crystal-stabilized oscillator). These latches feed into a pair of K561ID1 (4028) BCD-to-decimal counters controlling the memory chip selection, with an additional output for addressing the upper bank of the firmware memory.

    The tempo is dictated by the KR580VI53 (Intel 8253) programmable timer circuit on the main data bus L0...L7. Its clock output is fed back to the MCU on the IN1 port.

    The memory subsystem is gated with one of the three K561IR6A (4034) bi-directional registers. Fixed (predefined) rhythms are stored in a 27C16 EPROM marked "TAB". User-defined rhythms and songs are stored in three K537RU10 (HM6516) 8-bit SRAM chips with battery backup from four AA batteries.

    Then, there's the display and keyboard... The display uses full width of the data bus and the second 4034 register. It's split in half into segment control (anodes on the VFD) and digit control (grids). Anodes run through a 4056 inverter, grids run through a 4028 BCD-to-decimal decoder, a pair of 4069 and driver transistors. As for the keyboard, it's a 3 rows and 10 columns matrix. Columns are multiplexed from a 4028 fed from the upper nibble on the main data bus, and rows feed into buffers whose outputs feed into the IN0, IN2 and IN3 ports of the MCU.

    The last 4034 register controls the data flow to the DAC board.

    I still don't think I fully understand the system design on the PSR, especially the sample memory addressing (I haven't reverse-engineered that part), but it's a very interesting piece of Soviet microcontroller technology. Back in 1989 when it was designed, it must have been cutting edge technology in the USSR.

  • Videos on the Lell PSR

    Keri Szafir • 08/27/2023 at 20:12 • 0 comments