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CBJT Logic

Complementary bipolar junction transistor logic - like CMOS, but with NPNs and PNPs

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This project is about an experimental logic circuit topology using complementary BJTs in place of N- and P-channel MOSFETs in traditional CMOS circuits.

It may or may not work.

The idea comes from a simple mistake that apparently I was not the only one to make. About 20 years ago, I decided to design a discrete audio amplifier. Not having thought about it for a while before that, I got confused about the emitter-follower output, and made something like this:

At first, I couldn't figure out why the transistors got so hot. A co-worker who had previously designed audio amps for a boutique audio house pointed out that I had the transistors reversed; these were common emitter switches, not followers. In this configuration, once the supply voltage exceeds about 2*Vbe, the transistors bias each other on and draw lots of current. @esot.eric mentioned a similar learning experience regarding an H-bridge design from around the same time period :-)

At some point, I wondered what happens with supply voltages less than 2*Vbe - then, the circuit looks a lot like the classic CMOS inverter. I didn't do anything with it at the time, but the subject of unusual transistor circuits recently came up in another thread. It seems like there's enough interest to make this into an actual project...so here goes.

  • No, it's not that fast

    Ted Yapoa day ago 22 comments

    I stayed up pretty late looking at this stuff - it just didn't make sense. Finally, after playing with the simulations, I found something. The complementary NPN/PNP pair can switch very fast if it is switched continuously - like with a 50% duty cycle pulse. This somehow keeps both transistors biased, or keeps them out of saturation, or something, that allows them to switch very quickly. After a period of time this "magic quality" wears off, and they switch slowly again. I don't have a full explanation yet, but I've seen it in simulation and on the hardware now. I started with the simple inverter circuit again: here simulated with 1 nF and 100 pF caps:

    when you drive the 100 pF cap version with a 50% duty cycle square wave, you can get it to go 25 MHz (the limit of my current testing setup). With duty cycles other than 50%, the waveforms fall apart. Here are some scope shots for a 3 MHz input with various duty cycles. Yellow (lower trace) is the input to the inverter; cyan (upper trace) is the output.

    30%

    40%

    50%

    60%

    70%

    80%

    This is not just a case of minimum pulse widths - for example, here's the same circuit driven at 10 MHz with 50% duty cycle. The high time and the low time are both shorter than the 30% and 80% duty cycles above, but there's no problem at all with the output:

    The same thing happens with the 1 nF capacitor, just at different frequencies. This effect is also present in the ring oscillator, which naturally assumes around a 50% duty cycle, so it is able to oscillate very quickly.


    Something is happening in the transistor pair that I don't understand. I don't think the effect is really due to the duty cycle - I suspect that a recent pulse makes the pair faster for a period of time. If another transition happens within this window, the pair will remain fast. Once the effect has worn off, the pair will be slow for the next transition. I can't fully explain what is happening inside the transistors yet, but I see the same effect in LTspice, where it's much easier to make measurements, so I have a shot at figuring it out.

    The real bummer is that this invalidates all the previous speed testing. I haven't fully re-run the tests yet with isolated pulses instead of square waves, but a quick look at the scope puts the propagation delays in the 25-35ns range. It's not quite as bad as a CD4001, but it's no match for even the 7404.

  • Looking for the Goldilocks capacitor

    Ted Yapo2 days ago 4 comments

    UPDATE: the speeds measured here don't represent the true switching speed of these gates. See this log for more details.


    I initially settled on 1 nF speedup capacitors because they seemed to perform better in simulations - which were done with lower-frequency signals. The value did seem large at the time, but it seemed to work OK in practice, even though the ring-counter simulation would go much faster with smaller capacitors. I finally got around to trying smaller capacitors on the real hardware. With 100pF caps substituted for the old 1 nF's, everything goes more than twice as fast (with a catch, discussed below). The ring counter went from around 10 to 25 MHz:

    This frequency implies an average propagation delay of 3.92 ns. The scope measures 4.0 and 4.9, but may be confused by the under/overshoot. In any case, it's more than twice as fast as the previous circuit which had around 9.5ns of average propagation delay. A 74AC04 inverter has a typical propagation delay of 3.5 (TPHL) or 4.0 (TPLH) ns. This silly CBJT logic has gone from 74HC speeds to 74AC. Or so it would seem.

    What's the catch?

    Knowing my luck, there has to be a problem somewhere. It didn't take long to find it, either. At lower speeds (when driven with the signal generator), the waveforms fall apart - I saw this behavior in the simulations, too, which made me think larger caps were necessary. For example, a chain of inverters driven with a 1 MHz squarewave looks terrible (below, left). The same inverters look fine with a 2 MHz input (below, center), and OK to the top of my generator at 25 MHz (10 MHz shown below right) - some of that ringing is the ground leads on the probes; I was too lazy to solder on Z0-probes.

    100 pF just isn't enough at lower frequencies, which is bizarre, because it should be all about edges. Did I screw up and have the DDS set for a sine wave output?? Is the DDS edge rate lower for lower frequencies? Now I'm going to have to re-check when I get a chance - maybe this is something simple. It would be convenient if this bizarre behavior at low frequencies just went away :-)

    And the NAND?

    The NAND gate performance was also improved with the smaller capacitors - at least for higher frequencies. Driving the lower input showed a 3.3 ns TPLH and a 6.3 ns TPHL (the 74AC00 has 6.0 and 4.5 ns at 5.0V, respectively):

    With the upper input driven the NAND shows a 3.0 ns TPLH and a 6.3 ns TPHL - the input speeds are now basically symmetrical unlike with the 1 nF speedup caps. This is good.

    Oh, and if you drop the input frequency to 1 MHz or below, everything falls apart again. At DC, things work fine, as expected. I didn't measure the range of frequencies for which it's screwed up. I think this needs more bench time.

    It's another mystery!

  • NAND Issues Resolved

    Ted Yapo4 days ago 10 comments

      Yes, it was poor layout on the prototype. A long alligator lead used to pull one NAND input high had enough inductance to resonate with the input network and cause problems. I was able to simulate it in LTspice by adding an inductor where the long lead was. The yellow trace is the base of the upper NPN, and shows ringing like I saw on the hardware:

      The 200 nH value was a complete guess - the actual inductance would depend on how I draped the alligator lead on the workbench, but the qualitative behavior was the same as I observed.

      To fix the problem, I tied the upper input high with a very short wire. The circuit doesn't show the resonances anymore, but the propagation delay is still relatively long and somewhat sensitive to input pulse width. For instance, with a 1 MHz input signal, the propagation delay is around 16.5 ns, rising to 19.7 ns at 10 MHz:

      On a longer timescale, the 10 MHz output still looks usable - I think you could go even higher:

      Edge Rates

      The fact that this circuit had issues with long leads on a "DC" input made me wonder about the edge speeds - that's what determines how much you have to worry about layout. The conservative rule of thumb is that you have to treat wires electrically longer than 1/6 of the transition time as transmission lines and terminate them at one or both ends to suppress waveform-distorting reflections. So, I decided to measure the edge rates.

      In the book, "High Speed Digital Design: A Handbook of Black Magic", Johnson and Graham describe five methods for estimating the rise time of logic signals:

      1. Differentiating the step response to yield the impulse response then taking the standard deviation
      2. 10%-90% direct measurement
      3. 20%-80% direct measurement
      4. Center slope measurement
      5. Maximum slope measurement

      (1) is interesting but too involved for now. (2) and (3) are complicated by the ringing, overshoot and odd shape of the waveforms. That leaves (4) and (5), which measure the slope of the rising edge, either at the center of the edge, or at the position of maximum slope. I just used cursors to measure the slope somewhere around the middle:

      The measured slew rate is 440 mV / 960 ps = 0.458 V / ns. According to this site, this is about half the slew rate of 74HC logic at 5V supply, which is about 0.9V/ns. But, the supply here is 1.1V, only 22% as high as the 74HC. According to Johnson and Graham, this translates into a CBJT rise time of:

      The same calculation for 74HC logic at 5V supply yields 5.5ns rise time, which agrees with 5ns figures I've seen quoted elsewhere. So, CBJT logic has edge rates about twice as fast as 74HC. While at first this might sound good, it means complications for laying out projects with CBJT logic. Light travels 72cm in 2.4ns, so you might have to treat wires as short as 12cm as transmission lines (assuming velocity factor = 1). You could add some more parts to slow the rise time (a simple RC network on the output would do it), but it detracts from the simplicity of the design. Maybe you can just add an extra RC at the output when you have a long run to drive.

  • NAND hardware tests

    Ted Yapo5 days ago 9 comments

    UPDATE: the speeds measured here don't represent the true switching speed of these gates. See this log for more details.


    I built a test jig for the simple NAND gate design. In order to drive it with "native" logic levels and impedances, I buffered the output of my signal generator (set to 1.1 V output amplitude) through a string of four inverters. This should produce close to a real CBJT drive for testing the NAND.

    The gate design is as it was before: two 2N3904's in series on the low side, with two 2N3906's in parallel on the high side. I tested and simulated with a 1.1V supply.

    At DC, the NAND gate works as expected. To test the high-speed performance, I drove one of the inputs while holding the other high. This turns the NAND into an inverter, and allows testing of the AC properties of the gate. Since the low-side transistors are in series, the two inputs are not identical - this caused the funny threshold seen in previous DC simulations.

    The upper input behaves roughly as expected with the lower input held high. Here's the waveform at the upper input (yellow) and the output (cyan) when driven at 1 MHz:

    I measured the propagation delay as 9.5 ns for the H->L output transition and 4.7 ns for the L->H using cursors. The scope's auto-measurement came up with 7.48 ns and 4.5 ns for the same delays. Close enough - and not bad, really.

    Testing the lower NAND input was much more interesting. There was a much bigger difference between the two propagation delays. Again, testing with a 1 MHz input signal, I measured 5 ns for the propagation delay when the output was going L->H - about the same as the upper input. But, the propagation delay for the other transition (H->L) was 20.7 ns, much longer than the upper input! Here's the L->H at ns delay:

    vs the H-> at 20 ns:

    I found this odd, partly because I hadn't seen any evidence of this in LTspice simulations. There, the delays are roughly identical:

    Two things come to mind: it could be bad spice models or parasitics in the layout. But playing around a bit found something even more odd - the delay depends on the input pulse frequency. At 1 MHz input, the delay was 20ns - this grew to a maximum of around 40ns with a 5 MHz input, but then the delay abruptly dropped again at 6 MHz! It was also clear that there was some instability involved - you can see in the the 6 MHz cyan trace (lower right). Here are 1, 3, 5, and 6 MHz plots. The output also peaks above the supply voltage before the transition ( you can also see this in the simulation above).

    I probed around a bit, and found the problem (but not the solution) - there is some odd resonance on the node between the two 2N3904's. Here are the waveforms at that node (cyan) at the same frequencies:

    You can see that the ringing starts when the input signal goes low. For long pulse widths, the ringing has died down by the next transition. For shorter widths, the ringing can interfere with the next edge, extending the delay time by an amount that depends on what phase of the ringing the edge coincides with.

    I still don't know where that resonance is coming from. It doesn't happen in the simulation. I'll have to spend some more time with the board to figure it out. I think this can be fixed. Maybe it's just poor layout on the prototype.

    Even if this is an unavoidable feature of these logic circuits, this behavior will just limit the maximum usable clock frequency.

    Misc. Observations

    It was a bit of a mystery how the output stage switches so quickly - shorter than the transistors should be able to turn off. I looked at the simulation closely - the transistors are still slow to turn off, but the opposing one turns on quickly and dominates the output. This causes some huge shoot-through current spikes in the output stage. It may be enough to warrant a bypass capacitor per output pair. This is just something you'd need to work around if you wanted...

    Read more »

  • Speeding Up the NOT Gate

    Ted Yapo01/10/2017 at 02:04 22 comments

    UPDATE: the speeds measured here don't represent the true switching speed of these gates. See this log for more details.


    I played with the inverter simulation a bit - before testing the speed on the NAND gate, I figured I'd get things straight with the NOT. Adding the base resistors drops the power consumption as expected, but also dropped the oscillation frequency from 2.4 MHz to about 500 kHz. OK, I'll add the speedup caps. Simulations pointed to 1nF as a good value - which seemed large to me, but works OK on the board:

    With the 1k base resistors and 1nF speedup caps added, I tested the ring oscillator at a bunch of different voltages. I hooked channel 2 (cyan trace) to the power lead to label the images with the supply voltage.

    550 mV

    Again, I saw oscillations down to about 0.4V supply voltage, but things only started to stabilize above 500 mV. Here it is running at about 5kHz.

    707 mV

    This logic is probably only truly usable above 700mV (at the temperature I tested at - whatever that was). The circuit runs at 796 kHz, implying a gate propagation delay of 12.5 us, with a rise-time of 70.5ns (fall time not captured).

    808 mV

    By 808 mV, the speed has really picked up: f = 3.7 MHz, tpd = 27 ns, trise = 11.5 ns, tfall = 15.5ns. I forgot to measure the current.

    Note that those peaks on the top and bottom are above V+ and below ground - I forgot to move channel 2's reference to match channel 1.

    903 mV

    The speed has doubled now. f = 7.2 MHz, tpd = 14 ns, trise = 9.5 ns, tfall = 9.5ns, current = 4 mA / gate

    1.007 V

    A more modest speed increase. f = 9.5 MHz, tpd = 10.5 ns, trise = 10.5 ns, tfall = 10.5 ns, current = 8 mA / gate.

    I'm not sure I trust the scope's auto-measurement of rise and fall time with these waveforms. Next time I'm in the lab, I'll turn on the cursors and see exactly what it's measuring - although 1/5 of a division is 10 ns, which looks about right.

    1.102 V

    A little more speed. f = 10.51 MHz, tpd = 9.5 ns, trise and tfall about 10ns (scope auto-measurement screwed up), current = 12 mA / gate. This is probably the best voltage to run at.

    1.210 V

    Not much speed increase, just consuming more power. f = 10.58 MHz, tpd = 9.5 ns, trise = 10.5ns, tfall = 10.5ns, current = 18 mA / gate.

    1.306 V

    Speed reduced slightly, still more power consumption. 24 mA / gate now.

    1.404 V

    Less speed, more power - 30 mA / gate. The waveforms look superficially nicer, but at the cost of more than 3x the power used at 1.1V and a little less speed.

    Summary

    It looks like these inverters, with 1k base resistors and 1nF speedup caps, work best at around 1.1V supply. At this voltage, they show a propagation delay of about 9.5 ns. A look at the 74HC04 datasheet shows a typical 9ns tpd at 4.5V supply, which drops to 7ns at 5V supply. Amazingly, it would appear that this simple inverter is almost equivalent to 74HC logic in terms of speed. It doesn't seem like it should be...

    When I get a chance, I'll wire a 5/6 of a 74HC04 into a similar ring, and see what that looks like.

  • CBJT NAND Gate

    Ted Yapo01/09/2017 at 01:17 11 comments

    Here's a first try at a NAND gate. I took @Yann Guidon / YGDES's advice and went series on the bottom and parallel on top. If it works, the project is a success in some sense - every other gate can be constructed from NANDs. I've only simulated it so far.

    It's a straightforward adaptation of a simple CMOS NAND. I simulated the supply at both 0.8 and 1V, and it seems to work at either one, although a little better at 1V. The base resistors limit the input currents - these should have been on the inverter inputs, too. Because of the "stacked" input stage, the inputs are not symmetrical. For instance, here's the output voltage vs the top input with the bottom input held at logical 1 (1.0V):

    With the bottom input high, the NAND gate works like an inverter for the top input. And it looks like a pretty good one. The results aren't quite as good with the inputs reversed:

    Here, with the top input held high, the threshold for the bottom input isn't great. Still, if you specify the Vih parameter (minimum high input voltage) as maybe 0.65V, then it should be fine.

    I think this should be workable as a logic gate. I don't know about performance yet.

    AND Gate

    If you add another inverter stage to "clean up" the output, you get an AND gate with very nice thresholds on both inputs. Here's the circuit:

    and the output with the top input high and the bottom swept (the "bad' curve above):

    The output inverter produces nice thresholds for both inputs; their transfer functions are now basically identical.

  • First Test

    Ted Yapo01/08/2017 at 17:26 15 comments

    I decided to test the idea with a ring oscillator. After seeing that five inverters would oscillate in a SPICE simulation, I heated up the soldering iron and made this:

    there are five inverters based on the original circuit:

    each one has a 0.47uf supply bypass capacitor. The circuit starts to oscillate at about 0.4V, but is wildly unstable. At 0.8V, it draws 30mA with stable oscillation:

    The oscillation frequency is 2.4 MHz, equal to a period of 420 ns. This implies a propagation delay of 42ns per inverter.

    There are a lot of issues that would have to be solved before this becomes a usable logic family, but it's a start.

    If we can figure out how to make either an AND or OR gate, we'll at least be logic-complete, then it's a matter of details.

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Yann Guidon / YGDES wrote 01/11/2017 at 10:26 point

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Ted Yapo wrote 01/11/2017 at 12:54 point

Interesting - people have been here before (which isn't too surprising).

This allows a wider range of supply voltage, and reduces power consumption, although a quick SPICE test shows about 700ns of delay with no capacitors, which decreases to about 50ns with capacitors.  But that's just SPICE, and with no attempt to optimize anything.

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Yann Guidon / YGDES wrote 01/11/2017 at 21:33 point

I hope your tests will show interesting performance ;-)

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Ted Yapo wrote 01/10/2017 at 03:26 point

I found a link to the original article:

https://dl.acm.org/citation.cfm?id=1457779&CFID=714740953&CFTOKEN=69684497

those with access to the ACM library can read it (I no longer belong to the ACM or the IEEE - ask me about it sometime).  Anyway, I signed up for a free trial of a service called deepdyve that lets you read (but not download) this article - and many others from that era.  I can't justify paying for it, but I can read them for the next two weeks :-)

I'll post any interesting finds...

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Yann Guidon / YGDES wrote 01/10/2017 at 03:31 point

screenshots ?

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zakqwy wrote 01/09/2017 at 14:46 point

i will follow any project with such excellent soldering techniques.

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Ted Yapo wrote 01/09/2017 at 23:54 point

Thanks!

I actually got an OLFA 9mm knife that you recommended for Christmas, but haven't had a chance to try it on copper clad yet :-)

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zakqwy wrote 01/10/2017 at 00:31 point

I think you'll like it -- I usually go for a +/- 30 degree groove (i.e. two cuts to form a triangular wedge) with a ~45 negative rake angle, if that makes sense. I also built a little finger grip out of FR4 that slips over the knife since it's a bit on the narrow side. When soldering to large ground planes (as you are in this post), I've found it's quite handy to quickly cut 3 grooves around the intended location as a thermal relief--makes the soldering much easier.

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oshpark wrote 01/10/2017 at 00:06 point

We appreciated how much you love soldering after listening to the last The Amp Hour episode :)

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Ted Yapo wrote 01/10/2017 at 00:53 point

Thanks for the tips; I'll try that.

I bought a pair of cut resistant gloves to try also (on the non-dominant hand).  We had a blender incident here last month that resulted in nine stitches to my better half's left index finger, and it has made me reconsider all the blades we use.

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Yann Guidon / YGDES wrote 01/08/2017 at 19:23 point

copy-paste from the original thread: https://hackaday.io/project/18868-improbable-secret-project/log/50780-open-collector-fail-the-atx-power-switch-saga-continues/discussion-73557

____________

such thing could be called "LVDCTL" : Low-Voltage Direct Coupled Transistor Logic.
I can suppose it hasn't been implemented for several reasons such as :
- poor noise immunity
- those base currents that can't be controlled
- transistors were too leaky and inconsistent performance, binning would be a nightmare
- it's better to have one reference than two, less confusion and better bargaining power when ordering 1M parts
- maybe it's not as fast as other topologies

____________

now it seems that Baker used resistors to control the base current, which I think is a good idea(tm)

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Yann Guidon / YGDES wrote 01/08/2017 at 17:24 point

Do you remember that PDF that @esot.eric sent about DCT ?

https://www.computer.org/csdl/proceedings/afips/1958/5052/00/50520022.pdf

Well, scroll to the LAST page and there you have it !

Unfortunately only the first page, with the diagram, is available...

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Ted Yapo wrote 01/08/2017 at 17:31 point

Yes!  I didn't see it there before.  Maybe we can find the other pages somewhere

The R.H. Baker who wrote that article is the same Baker from the Baker clamp circuit(s) I've enjoyed playing with.

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Yann Guidon / YGDES wrote 01/08/2017 at 17:35 point

yes, saturation will be an ennemy to combat :-D

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Yann Guidon / YGDES wrote 01/08/2017 at 17:39 point


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esot.eric wrote 01/09/2017 at 03:32 point

hah! How'd I miss that?

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Yann Guidon / YGDES wrote 01/08/2017 at 17:18 point

I'm sure a better performance can be obtained by adding ideas from nonsaturating current steering circuits. The current and voltage are probably too high, adding a resistor in series should probably make it a bit faster (along with a capacitor in parallel)

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Yann Guidon / YGDES wrote 01/08/2017 at 17:16 point

Well, from the point of view of your first try, it works :-D

Now the challenge is to make a MUX.

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