Signal level compatibility tests -

XC9536XL CPLD   NMOS Z80  Noise Margin
Low  Out 0.4V < 0.8V      0.4V
High Out 2.4V > 2.0V      0.4V
Low  In  0.8V > 0.4V      0.4V
High In  2.0V < 2.4V      0.4V



XC9536XL CPLD   CMOS Z80  Noise Margin
Low  Out 0.4V < 0.8V      0.4V
High Out 2.4V > 2.2V      0.2V
Low  In  0.8V > 0.4V      0.4V
High In  2.0V < 2.4V      0.4V



Z80  CPU (NMOS) Max 8 MHz
Vil = < 0.8V
Vih = > 2.0V
Vol = > 0.4V
Voh = > 2.4V
Iol = 2mA
Ioh = -250uA
Ii  = 10uA



Z80 CPU (CMOS) Max 20 MHz
Vil = < 0.8V
Vih = > 2.2V
Vol = < 0.4V
Voh = > 2.4V
Iol = 2mA
Ioh = -1.6mA
Ii  = 10uA



XC9536XL CPLD Vio = 3v3
Vcc = 3.0V - 3.6V
Vol = < 0.4V
Voh = > 2.4V
Vil = < 0.8V
Vih = > 2.0V
Iol =  8mA
Ioh = -4mA
Ii  = 10uA

Conclusion -

These chips are compatible. The weakest point is a high from the CPLD to the CMOS Z80 where the noise margin is only 0.2V

I have two plan 'B's for this issue -

1) I have both 3v3 and 3v6 LDO voltage regulaors in the same package so that if I have trouble with the CMOS CPU then I can run the CPLD with a 3v6 Vio to lift the Voh a little to improve noise margin.

2) I will ZIF socket the CMOS CPU so that as a last resort I can remove it and replace it with a NMOS CPU

As the signals between the CPLD and CPU will be short (on one card), I am not really expecting that the 0.2V margin will be a problem.

Perhaps as a third backup I could design in a regulator on the CPU board to provide the 5V Vcc from the 12V rail so there are no issues with the Vcc being a bit low after coming from teh backplane. The CPLD will already have onboard regulation.

Short glossary of terms -

Vo - Voltage output

Vi - Voltage input

h - high

l - low

Io - current output

Ii - current input offset

Vio - IO voltage for CPLD

Vcc - chip supply voltage