2019-05-30

I'd been putting this project off for a while because it is very complicated to get fully working and I have no known-good firmware specifically for it. I considered porting a monitor but a BASIC interpreter would be more impressive. Grant Searle's minimalist 6809 design has Microsoft BASIC and the same 6850 ACIA serial chip. I would still need to reassemble the firmware source code with different addresses for this chip.

Grant's source code uses Motorola style. Comments begin with an asterisk instead of a semicolon, or not at all if there is enough for the assembler to make valid instruction bytes already.

The assembler I use (https://www.asm80.com) uses the most common syntax it can for all processors. So I had to do a lot of editing to get it to assemble, and it is still not generating a hexfile identical to the one from Grant's site.

It occurred to me that I could program the GAL chips to put the memory map the same at Grant's design. I can then use Grant's ROM unmodified. Also, I don't have to get everything working at once. Just the CPU and serial port at first. Then the STEbus, which requires cycle stretching. The tricky bit is getting it back in sync with the ACIA and PTM chips, which require fixed cycle times.

If that proves too difficult for me then I may replace them with chips that have independent clocks, such as a real-time clock that can interrupt the CPU every second (for OS/9 and Flex operating systems), and the Zilog SCC which is a far more powerful serial chip.

Finally, I might also replace the serial chip with a USB module from FTDI. These have a really simple FIFO-like interface, and avoid the need for external RS323 to USB converter cables.

2019-05-31

Inserting jumper links, I notice the manual and circuit diagram are both version 1 issue 5, applying to version 1 issue 2 boards. I have a version 1 issue 1 board, lacking link areas J21 and J22. I can work around the differences.

2019-06-01

Finished porting Grant's code to use the online assembler syntax. Found one error, and other errors due to operator precedence which were fixed by brackets. Original source was all upper case, which make sense if the host machine only has upper case e.g. the 6809 CoCo and Dragon.

2019-06-02

Had a look at some other 6809 machines to see what their memory maps look like. E.g. the CoCo, Dragon, and Acorn 6809 card. Looks like operating systems really need a counter/timer to interrupt them at least once per second. The CoCo and Dragon don't have this but seem to manage without. The Arcom SC09 has a 6850 programmable timer module. The Acorn 6809 card has a 6522 which can generate interrupts and as a bonus provide parallel I/O for driving a printer.

I think a proper real-time clock would be better, providing interrupts and a useful clock/calendar.

2019-06-20

Stage 1, first attempt at programmable logic tried.
E and Q signals running at a quarter of master clock - correct.
Address, data and control signals flapping away, indicating the CPU is running even if it is garbage.
Nothing coming out the serial port, because the Timer chip needs to programming to drive the Tx/RX clock of the ACIA chip. Grant clocks his ACIA from the E signal, at 1.8432 MHz. My board has a 16 MHz crystal and 2 MHz E signal. I need either a separate baud rate clock or change the 16 MHz master crystal to a 14.7456 MHz crystal.

2019-06-21

14.7456 MHz crystal fitted. 6840 timer chip removed and E wired to TX/RX clock pins.  Still no sign-on message. Looks like I need to get the logic analyser out to see what the signals are actually doing.

2019-06-26

Logic probe showed the TX line was not valid TTL voltage. It was 0.9 volts. Dead buffer? Removed buffer, it raised to 5V. Replaced buffer, still 5V. Had it been in the wrong way round? Check the photo, yes it had. And my +/-12 source was dead.

2019-06-28

Read and Write signals modified....

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