06/08/2017 at 09:40 •
The Address Register panel has been installed:
The Address Register latches a 6-bit address from either the FC memory or the Program Counter. The output of the Address Register goes to the Address Mux/Decoder installed previously. Here's a short video of them working together:
Next up: the Program Counter
05/24/2017 at 09:13 •
See it cycling through the address space:
The bottom section multiplexes between 2 address sources: the address register and a manually-set address. The top section turns the selected address (blue lights) into a row/column selection for the memory (top right yellow lights).
I need some power splitter/extender cables before I can connect it to the FC memory, that's a project for this weekend.
Next panel: the address register itself.
05/06/2017 at 04:37 •
The next board to be added to the system - it selects between Address Register and Manual Address entry, and converts the selected address to Row/Column selection in the core memory. Pictured here with 6 partially-complete 2:1 mux modules yet to be installed:
Note that all components get a liberal application of cat hair before installation.
04/12/2017 at 09:01 •
An architecture and name change: the T-1 is now the ED-64, and it is no longer a stack machine. The changes were made for several reasons:
- I decided I really wanted to be able to load programs into the memory manually from the operator panel, and the Harvard architecture of the T-1 (and 10 bit program word) wouldn't allow that.
- For an 8-bit word formatted [Opcode][Address], a 2-bit instruction width means a 64-byte address space. Since I am avoiding multi-byte instructions, that means I only need to complete a single 64-byte core matrix (which I already have).
- Only 4 instructions drastically simplifies the control logic and ALU, while still allowing enough complexity to do interesting things.
- I got bored with the 'T-1' name!
11/18/2016 at 22:50 •
The emulator shield is done:
I've written a program in T-1 assembler that simulates rolls of a dice. It uses a 32-bit Fibonacci linear feedback shift register to generate a pseudorandom bitstream, which is sampled 3 bits at a time to produce a pseudorandom number from 1 to 6 (0 and 7 are discarded):
The 8-bit input port is just used to generate a delay.
I'll upload the code soon.
09/14/2016 at 06:55 •
I've designed a shield for my Arduino Mega 2560, that will provide the input and output ports. Once plugged in, the simulator (emulator?) will be able to do real-world I/O. Not much to it, just 8 LED drivers and 8 debounced SPST toggle switches:
09/13/2016 at 09:01 •
Just a minor update - I have done some 'simplification': halved the instruction set to 8 instructions total, and reduced the ALU to 4 functions. This will allow a significant reduction in the amount of hardware I'll need to make, while still allowing meaningful programs to be written. I'm also taking some inspiration from the Kenbak-1 - the I/O has been reduced to one input and one output port of 8 bits each. If this seems extreme, recall that the T-1 is more or less an 'art project' - I'm not trying to replace a desktop PC.
And there's always I2C/SPI :)
08/25/2016 at 07:47 •
I have written an instruction set simulator for the T-1. It is an arduino sketch, and runs on an Arduino Mega 2560, using the onboard UART to provide the operator interface. Current simulator functionality includes:
- Single step and continuous execution modes
- Execution breakpoints
- Inspect and modify stacks, system RAM and code memory
- Inspect and modify top-of-stack register and program counter
- Halt on stack under- and overflow
To get a program into the simulator, I have written a shell script that does the following:
- Calls the ASL assembler to assemble the code
- Calls P2HEX to convert the assembled code into an ASCII hex format
- Converts the hex file (using awk) to a header file that is an initialised C array of unsigned ints
When the sketch is uploaded to the arduino, the header file is included and provides the instructions for the simulator.
The simulator will allow me to experiment with different instructions, and allow me to test programs before I commit to wiring them.
Here's a screen capture of the main menu:
and a code memory dump:
08/12/2016 at 23:11 •
I now have a functional assembler for writing T-1 code (in order to generate wiring patterns It supports macros, which will help a lot, given my restricted instruction set. It is based on the AS macroassembler by Alfred Arnold. It is a crossassembler that supports many processor families. Arnold includes straightforward instructions in the manual for adding new processors, which I have followed to add T-1 support. Here's an extract of the list output for some simple looping code:
1/ 0 : cpu t1 2/ 0 : 3/ 0 : =0xA counter equ 10 4/ 0 : 5/ 0 : 000A push counter 6/ 1 : 0304 loop1: dec 7/ 2 : 0309 skz 8/ 3 : 0101 jump loop1 9/ 4 : loop2: 10/ 4 : 0104 jump loop2 11/ 5 :
I am currently working on an instruction set simulator, which will run an on arduino mega 2650 board (the same board I use to test logic modules after I make them). The arduino will take the assembler output and simulate execution, allowing me to test the program functionality, inspect stack and memory contents etc - before I commit to handwiring a ROM board!
04/20/2016 at 09:17 •
The T-1 project blog is beginning to get a bit unwieldy, so I have decided to document the computer sub-systems as separate projects, and use this one as a 'top level' project to tie everything together.
The ferrite core memory is the first sub-project, it will be followed (eventually) by the ALU, program memory, etc. as I work through and build them.