09/18/2015 at 00:26 •
The first in a series of logic modules has been completed: a D-type flip flop with asynchronous SET and CLEAR, and tristateable output. It is a 6 NAND-gate arrangement similar to the 74S74. The PCB is 4 layers, and the transistors are MMBT3904s with BAT54 Baker clamps.
I've simulated it with LTSpice and it should be capable of a least a couple of MHz.
This is Rev B. Rev A worked, but I decided to make the module sides slightly concave to assist insertion and removal, and to curve the top - I think it looks nicer. I also decided to go for an edge connector - the 44-pin Multibus II.
And yes, that is a kludge wire near the top!
Here are 18 waiting to be tested:
Now I need to build a jig to test them!
09/22/2015 at 08:48 •
The Data and Return Stacks will each consist of a 64-byte ferrite core array. 64 bytes requires a 6-bit pointer to address the stack contents. This 6-bit pointer must be decoded to select one of 8 columns and 8 rows in the core matrix.
Below is a closeup of some of the edge connectors I will be using throughout this project. They are 44-pin Multibus II connectors from Digikey:
09/27/2015 at 06:27 •
The jig to test the flip-flops has been finished:
The jig is basically an Arduino Mega 2560 and a Protoshield. Press the 'GO' button and the flip-flop under test is checked for /RST, /SET, D->Q, and output tristate functionality. I've tested the 18 flip-flops I made earlier and found 4 failures - more than I'd like. But the jig indicates at what point in the testing that the failures fail so troubleshooting shouldn't be too difficult. And I have 14 which are ok!
10/05/2015 at 06:54 •
The current task is to get the stack address decoder boards populated with the required logic modules. The flip-flops have been made and tested, next up are the AND gates. The PCBs are currently being made by pcbway. Here's the schematic for a single AND gate (there are 4 of these on a module board):
According to LTSpice, this gate design should be good for several MHz, with an average current consumption of 10mA (driving 1 downstream gate input).
Here's a screencap of the PCB (power and ground planes turned off):
10/11/2015 at 04:23 •
I have opted to mount the electronics in a frame constructed from Openbeam extrusions. The extrusions themselves are from Makershop here in NZ. The frame will consist of 7 facets fixed in a semicircular arrangement. Each facet will hold vertically 3 backpanels. This will provide a good view of everything and allow easy access to wiring.
Shown in the photo are brackets for mounting 2 horizontal extrusions to a vertical one at 30 degrees, a 90 degree corner bracket and a bracket for butting a horizontal extrusion against a vertical one.
10/12/2015 at 06:04 •
20 AND module boards now waiting to be populated:
10/17/2015 at 22:41 •
It's missing a few screws (like its creator), but the frame for mounting the boards is largely complete:
Each 'cell' in the frame can carry a 177mm wide by 275mm high PCB. The inter-module wiring will be run along the interior sides of the beams, and the logic modules, memories and operator interface will face the exterior.
Here are a couple of shots illustrating how the module panels are held in the frame:
There is provision for a top and bottom cross-beam to give the structure extra rigidity if I decide it needs it:
11/03/2015 at 06:05 •
There has been a hitch in arranging a stencil for the AND gates (thanks for nothing, Paypal) so I have hand-soldered the first one to test the design:
Next up, a jig to test finished AND, OR and NAND gates. I also intend to whip up a carrier board to do some speed and propagation delay tests.
Also, I have repaired the 4 faulty flip-flops from my first batch of 20. The usual problems - diodes around the wrong way, missing resistors.
11/05/2015 at 02:17 •
I modified the FF jig to test the AND gate I had soldered. The jig tests each gate with all 4 binary combinations of input, and looks for the correct binary result. 4 green lights = 4 good gates:
Each gate has a red LED to indicate output state.
I also did some speed tests. Here's a gate output waveform with both inputs driven by a 1 MHz square wave:
and at 2 MHz:
some over/undershoot present but not too bad. There is provision on the module for loading some capacitance to smooth it out if necessary. I would have liked to have driven it faster to find its maximum switching speed but my signal generator only goes up to 2 MHz.
Finally, I wanted to see some lights blinking so I wrote some crappy arduino code for the jig to do it:
11/23/2015 at 07:47 •
The first NAND module has passed testing:
A screencap of the schematic of one of the gates (1/4 of the module):
As you can see, it is basically my standard complementary-driven totem pole output, with a couple of schottky diodes in a wired-AND input configuration.
Almost ready to start populating the stack address decoder panels....!