Video design made simple

A project log for ZynqBerry

Xilinx ZYNQ based RPi

Antti LukatsAntti Lukats 04/17/2016 at 12:412 Comments

The big picture in IPI BD:

Visible are the ARM CortexA9 hard core, and blocks for Audio, Camera and HDMI Display

The audio block, is implemented based on IP compatible to Analog devices SPDIF IP Core, so we can reuse eixsting drivers. The IP Core has been modified to expose not SPDIF but AXI4-Stream as audio output interface, what is connectef to AXI4-Stream to PWM IP Core. Please note that this IP core is using Cortex A9 DMA channels, the DMA engine is not created in the FPGA.

HDMI Output is also rather simple, Xilinx Video DMA is used to to get framebuffer data from DDR memory, this video streami is converted to color format supported by Linux simple framebuffer drivers, and then it sent to HDMI serializer. VDMA init is done in the FSBL, also logo is loaded by first stage bootloader so it appeary very quickly during startup.

MIPI CSI2 camera processing path is bit longer, it is first converted from CSI2 signals into intermediate PPI Interface also defined by MIPI alliance as the MIPI PHY interface. PPI is then converted to AXI4-Stream. As next step the video data passes dual clock FIFO to move into system clock domain. Then the camera data is processed to convert RAW10 format into RGB. Before going to Xilinx VDMA IP Core the video data is resized so that it can directly be displayed on HDMI monitor.

Thats it folks.


patrickpoirier51 wrote 04/27/2016 at 12:31 point

Quite impressive, when you say '' video stream is converted to color format supported by Linux simple framebuffer drivers'' do you mean that you have implemented V4l2 Linux Driver for the Arm Cores ?

Will it be the same type of Driver interface that will expose the CSI2 camera ?

What Linux are you implementing?

Correct me if I'm wrong : USB, Uart, I2C are implemented, so SPI and some GPIO mapping are still missing to make a full blown ZB?

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helge wrote 04/18/2016 at 05:33 point

great work as always!

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