This board has not been described before but there is enough progress to do it now.
P5A has several functions but mainly, it's what transforms the operands into a result. This includes computing (add/sub/mul/SHL...), updating a couple of condition codes, assembling the operands from the different fields and even some I/O.
The board's dataflow starts with the SND and SI4 operands, which are correctly selected and latched. SND and SI4 are available on the read buses only briefly, because once they are read, the sequencer will read DST and CND (destination and condition) right away (when applicable).
SND is the operand that can be negated (for boolean operations, as well as SUB and derivatives like CMP, MIN/MAX...) so its value is latched right at the SND data read bus. The SND address (4 bits) may be reused as a destination address for the short instruction forms (but this is handled elsewhere).
SI4 is the operand that may be a register or an immediate value. Immediates may be 4, 6 or 16 bits wide in YASEP16, always sign-extended. Some MUXing is required in front of the latch. The MUX is controlled by a few bits of the instruction.
SI4 is a bit tricky because its value can come from both half-cycles of the instruction: a register value (form RR) or a sign-extended 4-bits immediate (form iR) can be written at the end of the first half-cycle, but this value can be overwritten if a) the instruction is a long immediate (form IR or IRR) or b) an extended form with short immediate (form iRR)
If the instruction is short, the SI4 register is not changed. If the instruction is long, only the 12 MSB are changed because the fields are designed to minimize bit shuffling.
The 4LSB are latched from a MUX2:
- when the Imm/Reg flag (instruction bit n°1) is 0, the SI4 read bus (bits 0 to 3) is chosen,
- when Imm/Reg is 1, the SI4 field (address field from the instruction, bits 12 to 15) are chosen.
The 12MSB use a MUX4:
- When the Short/Long flag (instruction bit n°0) is 0 (short form), select either the SI4 read bus (bits 4 to 15) when Imm/Reg is 0, else copy the SI4 adress MSB (sign extension).
- When S/L is 1 (long form), copy the instruction's bits 16 to 27 when Imm/reg is 0, else copy instruction bits 16 to 17, then pad the MSB with bit n°17 (sign extension)
I apparently forgot the RRR form but that's just a it more decoding logic, no datapath modification. Sequencing will be a bit tricky too but not impossible.
One extra MUX2 layer could be added to overcome the main issue of the YASEP ISA. Relative jumps are limited by the small width of the SI4 operand in extended form. The new ISA (defined in 2014) extends the imm4 field from 4 to 6 bits with a clever reduced-size "update" field but the range is still +31/-32 bytes, or +7/-8 long instructions only.
The range can be extended in two ways but they both need extra logic in the critical datapath to detect a iRR add with PC as destination and source (ADD x PC PC condition)
- The range can be extended from +7 to +8 by adding +1 through the carry input when the imm6 field is positive (bit n°5='0'). This makes sense because "ADD 0 PC PC" is useless.
- The range can be doubled with a MUX2 on SI4, that shifts the imm6 operand by one bit, because instructions have an even number of bytes.
These two methods are complementary but have side effects when put together. To effectively increment the shifted Imm6 value, the LSB (bit n°0) must be set to 1 so the carry-in of the ALU will ripple to bit n°1.
However, detecting the right condition uses gates and takes time. The first conditions are evaluated while the register set is being read so it's painless:
- Opcode : Add
- LSB=11 (extended instruction)
- SND address=PC (0)
However the second half of the instruction becomes critical:
- Aux flag (bit n°20) = 1 (imm6 present)
- DST = PC (0)
- MSB of imm6=0 (for the carry in and LSB setting)
Since this condition can only be found after the first nibble of SI4 has been latched, the shift must occur after the latch...