Cambridge-1 CPU spec: 4-bit word size4-bit adder (74HC283)8-bit data path8-bit address path8-bit memory word (4-bit instruction + 4-bit operand)40 Hz clock speed16 instruction ISAVirtualised control unit (using an Arduino Micro)Program loading (into...
Since the prop has 8 CPU cores, it can do many things at once, independant of each other, without interupts. Also each CPU core has 2 timers, and an A side and a B side, so a clever guy can (and did) make some neat stuff for us.
The instruction set for ECM-16/TTL homebrew CPU can be subdivided into several broad categories: - ALU operations on General Purpose Registers - MOVs - Loads of immediate values into registers - Loads/Stores via explicit (direct) address - Loads/Stores...
My try on the one page cpu challange, the cpu itself without the alu is just 48 lines of python code and is convertable to vhdl or verilog with the myhdl software/hardware (http://www.myhdl.org/) description language. The op-code is 8 bit wide and the...
CPU 4 Background. Weird CPU My first CPU (https://hackaday.io/project/12879-weird-cpu) was an 8 bit TTA (Transport Triggered Architecture). It has a front panel and sits happily on my shelf chasing LEDs in circles (such is the life of a simple CPU):...
This series of CPU's is based on the Scott Architecture ( from the book 'But How Do It Know' by J. C. Scott ) and modified by me.There are 4 types of CPU's I've designed so far;Schön Core Lite which is an 8 bit computer that is quite light on resources...
Just like other projects of this type, I think this is a great simple starting point to understand a CPU. It is one step simpler than the CHUMP design for example. Though not really practical for any real use, but shows the basic parts. If this were...
The ZX machines read the matrix keyboard by lowering 1 out of 8 upper address lines (A8..A15) and then read 5 bits of data in lines D0..D4 (as D5..D7 serve for other purposes). According to the Z80 manual during an I/O read cycle the time spent from...
Architecture Wikipedia article: Transport Triggered Architecture Since the CPU doesn't utilize microcode (I don't have an EPROM burner so one of the goals was to create the CPU without EPROM chips), it can do only one simple thing: move data during...
Many 8-bit processors and some 16-bit processors from 1970's and 1980's are packaged as 40 or 48-pin DIP which is easy to prototype, processors such as Z80, 6800, 6809, 8080, 8085, 1802, 6502 and some 16-bit processors with 8-bit bus such as 68008...
Demo session, uploading the bit file (which is inside the sys_180x*.zip) to Digilent Anvyl board, and running Monitor and Basic. Both the CPU and the TTY to VGA controller have been programmed using the microcode compiler.
New Planned Specs New architecture that leans more toward RISC, but has many similarities to x86 architecture. 64-bit 4 general purpose registers 2 pointer registers should be ABSURDLY FAST (for an FPGA) Still in the works.... Old Specs for early N016...
System Architecture: This device will operate mainly on the Z80, with an ATMEGA1284 microcontroller as a coprocessor to handle graphics, audio, and IO. Both chips are connected through an IO bus where the CPU uploads data to the MCU to do it's thing....
* This project is sponsored by PCBway, full feature custom PCB prototype service. https://www.pcbway.com/There are many prior examples of 4-bit CPU projects. For example, a 4-bit CPU (TD4 once again) by Fedor Gruzdev https://hackaday.io/project/161708-4-bit-cpu-td4-once-again...
An 8 bit RISC CPU for TinyTapeout. Tinytapeout combines 500 designs on a single IC to be taped out with the Open MPW-7. This offers the opportunity to actually get a design made on a real IC, but also comes with some constraints: Maximum allowed area...