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6139 Results for "%E3%80%8A%20%EC%98%88%EC%95%BD%EB%AC%B8%EC%9D%98%20OIO%E2%89%A1%E2%91%A7%E2%91%A389%E2%89%A183O%E2%91%A5%E3%80%8B%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8%EA%B2%AC%EC%A0%81%E3%82%88%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8ago%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8%E3%83%A1%EA%B0%95%EB%82%A8%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8eighty%20%EC%84%A0%EB%A6%89%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8%CE%BA%EC%84%A0%EB%A6%89%EB%A0%88%EA%B9%85%EC%8A%A4%E2%92%B2%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8%E3%83%A1%EF%BD%83%EC%84%A0%EB%A6%89%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8literary"

  • Finally, some publicity!

  • An article recently published on MOONGIFT, a Japanese developer site, has showcased RasDash! The article is entirely in Japanese and Google Translate won't accept the URL as it has special characters but YANDEX does. Below are some links and a basic...
  • Backplane

  • I decided that interface between ZIF-socket and host machine will be implemented with help of this antique ISA backplane manufactured in 1984 (I bought it for about $20 last month):I cut out it a little to remove part with pull-up resistors, because...
  • Draft Bus Layout

  • Here is a draft bus layout - 1 +5V +5V 2 +12V +3.3V 3 4 5 6 } 18 pins for other signals 7 8 9 10 11 12 REFSH RESET 13 M1 CLK 14 INT NMI 15 BUSRQ BUSAK 16 HALT WAIT 17 MREQ IORQ 18 RD WR 19 A14 A15 20 A12 A13 21 A10 A11 22 A8 A9 23 A6 A7 24 A4 A5 25 A2...
  • Changing the memory access model

  • In the past weeks, I did first draw the design in the Logisim simulator. The first few instructions were succesfully simulated. Then I started working on a Javascript assembler-simulator combination. While I've been making assemblers in the past,...
  • OPS ENUMERATED - Draft

  • This represents a complete OPCODE list with 14 Constants (int values) available and 10 Labels (byte values) available for creating subroutines. Constants were favored over Labels, but this is up for evaluation. NOP and HCF were both added to the official...
  • Control Board FPGA Pinout

  • I might be missing a few connections yet which I'll correct as I come across them, but here is the pinout of the XC3S250E FPGA on the control board.  Note that the SRAM and the Flash share an interface bus.  Also note that the JTAG interface...
  • [E1][T][M] Tetent with 1440px screen?

  • 1440x1440px resolution at 125% scalingWhat the screen would look like on Tetent (but sharper). This already makes me think back to my Windows Vista on PSP days, but I'm mainly imagining the future present of quietly chilling in bed while trimming down...
  • [E3][R] Transparent HMD Options on AliExpress

  • Realising that I had the simple yet inescapable choice to finally look into a strong and stable life-management system or chaos continuum, I started searching around on Friday 24th Nov when I said to myself "I feel that if I set the budget for the HMD...
  • Subtraction

  • SubtractionI have had a bit of a problem getting my head around subtraction and the borrow/carry flag. With some CPUs (such as the 6502) the carry flag is set and when underflow occurs then the carry flag is cleared. This works of course but makes JNC...
  • FAT32 File Format

  • When you search google for FAT file format you get tons of pages on formatting disks. It's harder to pull out the detailed format of the SD card. Wikipedia to the rescue (Design of the FAT file system). A less technical FAT32 Wikipedia page is File...