106 Results for "68000"

Loading/Running Tiny BASIC
Log from Retro 68000 CPU in an FPGA
The Motorola MC68000 Educational Computer Board (MEX68KECB) has a Tiny BASIC that is already assembled. Since the card is compatible with my FPGA design it loads nicely. Type LOAD on VDU portWaits on S-records from the ACIA portRunning PuTTY...

Improvements for the Cyclone V FPGA
Log from Retro 68000 CPU in an FPGA
The Cyclone V FPGA (PN: 5CEFA2F23) has a lot more internal SRAM than the EP4CE15. I was able to add 96KB of internal SRAM. Due to the TS2 memory map the new memory could not be contiguous with the lower RAM. That's because the Tutor ROM is...

Enhanced BASIC
Log from Retro 68000 CPU in an FPGA
Jeff Tranter also ran the Enhanced BASIC on his TS2 build. It loads into ROM on his card from 0xC000-0xCFFF. This card is compatible with Jeff's design (it's based on Jeff's design which is a copy of the Teeside TS2 board so any software that Jeff got...

TG68 Hardware
Log from 68K CPU with Frame Buffer on FPGA
This project is intended to be a software project but a description of the hardware is necessary as a reference to understand the resources available to the software. Features Runs on Altera Cyclone IV and V FPGA Cards68000 CPU32 MB SDRAMHost Serial...

Tick Tock
Log from Merlin
Following on from the interrupts work, I now have the RTC, a 100hz timer and millisecond 32 bit-counter up and running. The 100hz interrupt can be switched on or off, the millisecond timer starts counting at system start. That I think is the last of...

Step 1: Get free run!
Log from Yet Another 68k Homebrew Computer
Effectively `free running` of the processor is the state where it doing something without involvement from the outside. But first some basic info on the processors and execution of the code. CPU effectively doing following steps when powered on...

Benchmarks!
Log from rosco_m68k
Over on Discord, @Xark recently did some work on porting some old dhrystones to the rosco_m68k, which gave a feel for the performance of the board for the first time, and the results are encouraging! In Xark's words, we "blew the doors off an outdated...

Early Video Output Experiments
Log from RISCoVite
I'm currently at the stage of exploring this project in isolated parts, some of which I'm drawing in from my previous (unfinished) 68000 homebrew computer project.I had originally planned for the 68000 computer to have 800x600 VGA output with 12-bit...

TUTOR Loading S-Records Timeout
Log from Retro 68000 CPU in an FPGA
I tried to load a program using the S-Record loader built into the Tutor monitor using the LO command. The problem was that the board immediately timed out. The reason is TUTOR has a software loop which times out the load in 10 seconds and the FPGA...

Speeding up the CPU
Log from Retro 68000 CPU in an FPGA
The 68000 CPU IC had a pin called DTACK* (Device Transfer Acknowledge). When you grounded DTACK* the CPU ran at full speed. If you wanted to slow down the CPU for a slower external device you pulled the pin high until the device finished. The FPGA...

How fast can it run?
Log from 68000 minimal homebrew computer
Introduction Back in the nineties, I was worried if the system could run on 8 MHz. In the end, it did, but now I am curious about what the max speed is. The CPU is a MC68HC000 CPU rated for 16 MHz, but it is unlikely to reach that. The components are...

1616 TPAL analysis
Log from Applix 1616 Documentation
IC15, TPAL, Timing PAL We can see that pins 19,18,17 are a simple clocked counter. Other signals control DRAM, and other designs might provide a starting model. The RAM is interleaved VDU/CPU access, so the DRAM signals may only begin just after the...

CPU Choice
Log from T030
The next step in the project is choosing which CPU in the m68k series to use.I have a board from an old payment terminal with a 68008, but I quickly decided that 1 MB address space is simply not enough.In the attic I found and old Amiga 500 from which...

Timing explained
Log from STEbus I/O prototyping board
The STEbus was defined in the early 1980s, when a typical bus cycle for a processor and its support chips was about 1 microsecond. A 4 MHz Z80 took 3 or 4 clock ticks, and 8 MHz 68000 took 8 clock ticks. Memory chip speeds were about 300 to 450 ns, so...

AN1015 Redux
Log from Tiny020
Motorola has published an apnote, AN1015, describing a minimum 68020 system. Looking at it with today's better components, the appnote called for more parts & greater complex than is really necessary. I would rather do without PLD or CPLD--it tends to...

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