Here is how you can model a transparent latch in Logisim. https://en.m.wikipedia.org/wiki/Flip-flop_(electronics)#/media/File%3AD-Type_Transparent_Latch.svg. You don’t have to reset it. Just run INC to the D input and take the Q output to your AND gate. Then invert CLK and run that to the Enable input of the latch. That will prevent INC from changing at the AND gate while CLK is high.

That's got it.  Thanks a bunch @Drass .  This one was really stumping me.  When I first encountered the problem  my brain was telling me that a flip flop could fix it some how, but I couldn't quite figure out how.  When looking at the datasheet for the 573 I was worried that the common enable input might be a problem, but all my INC / DEC circuits for the register will be using the same clock so it is perfect.   

Awesome. Glad it's working @2-Zons . Yeah, you want to apply the same technique to all control signals that are being used to gate the clock -- a common enable is exactly what you want. Btw, you can achieve the same result with a D-type Flip Flop (74HC574), but you do have to clear those (which can be done mid-cycle with a low-going pulse to the  /CLR input).

Don't hesitate to hit me up with any other question as you go. Happy to help out. Cheers!

I thought it worked, but it didn't.   I implemented it in the register sub circuit and tested it.  It works at that level, in that only cycling the CLK will increment the counter.  Leaving the clock HI or LO and cycling INC had no effect (good).   But testing it out on my main circuit I have some weird effects.  Previously I was getting extra increments between cycles, which made sense to me because INC signal had a couple gate delays from CLK and would be slightly behind, causing an extra increment when INC was changing states.  Now it doesn't increment sometimes and does extra increments other times.  I'm not sure if it's bugs with Logisim or not.  

It's hard to visualize what's happening without seeing your schematic. Logisim does model these things pretty well though. Take a look here and try these circuits out in Logisim ... https://hackaday.io/page/5780-clocking-counters

I got it working before I saw you're reply.  I did a similar thing to what is shown.  I made a delayed clock signal using a bunch of gates, AND'ed it to the clock, and used that signal as a clock so that it would only be a short pulse after rising edge of main clock.  It works now.  I'll have to think about how I'm going to implement in actual hardware.  I will have to do some testing.

I agree with Drass that allowing INC to change only when CLK is low might be a part of the solution. You use the 193 counter with separate clk up/dn inputs. I read from a Nexperia datasheet that when one input is clocking, the other should be kept HI. So HI is the inactive level. Producing the clock inputs with a multiplexer is indeed tricky because the risk of producing non-intended clock pulses is high. Simulation will help here, but making a good simulation model of the 193 might be a challenge in itself.

I built a 193 in Logisim using the datasheet schematic.  I have my complete CPU design implemented and mostly working.  

Sorry for the negative point, I was looking for a way to sort this discussion chronologically. 

Btw I agree with both of you on the requirement for INC to change only on opposite (inactive) CLK edge.

Negative point is no problem. You just have to like all my projects :) ! Have a good 2019 !

Fantastic project @2-Zons. Here is a transparent latch: http://www.ti.com/lit/ds/symlink/sn74als573c.pdf. In your case, you would drive it with an inverted clock. 

Your suggestion could work, but be careful of when INC changes value. If INC ever goes from low to high while CLK is high, the MUX output will generate a rising edge. It depends of when your CPU changes internal state, but if it is on the rising clock-edge (which I suspect is the case for you) then control signals will likely be changing value right after the rising clock-edge. If so, you will get random increments on your counter. 

Thanks for the suggestions @Drass .  What is a transparent latch?   I think I've found a solution.  This is part of my TTL CPU project: https://hackaday.io/project/162659-8-bit-breadboard-cpu . My register is using a 2 to 1 MUX chip (74HCT257) for passing the U / D signals from the low byte to the high byte depending on weather it's a word inc/dec or a high byte inc/dec.  There are unused MUX's on the chip.

I can tie one input of the mux to gnd, and the other to CLK.  Switch the MUX with INC.  That way when CLK is LO the output won't change until CLK goes HI.   I hope that makes sense.  I will test this solution out and report back for anyone interested.

No, that didn't work.  Same problem.  Trying to figure out how to use @Drass 's suggestion.  Trying to work out how to reset the latch without more chips.

What type of register are you using? What control lines does it have?

This can happen when gating clock signals directly. A couple of thoughts: (1) allow INC to change only when CLK is low (with a transparent latch), or (2) use an flip-flop clocked by the rise of CLK to “let through” INC only at the rising clock-edge (i.e. the D input of the flip-flop will be INC). Use the Q output of the Flip-Flop to clock the counter (you’ll need to clear the flip-flop with a low-going short pulse to /CLR at the falling-edge fo the clock). Hope that helps.