Summary from the previous episode: as the number of registers grows, the power draw grows even faster (in N×log2(N) or so, depending on the aproach). If this can be reduced to N, the power draw could be greatly reduced.

This is actually possible, with minimal overhead but potentially some... complications.

The overhead is because instead of having a MUX2 tree, we simply use N relays to connect one output to the read "bus". So for 8 register as currently envisioned, there will be 8 relays per selector (instead of 7). Those relays will in turn be driven by other relays (the dreaded control signal fanout trees) which are not significantly larger than in the precedent version.

For a 16-bits ALU, there is a 2-level driver tree. Each register is split into 4-bits nibble with shared control lines (with a 10-12V power supply). They are in turn driven by a selector (inverted MUX) powered by the 10-12V supply.

The trouble is basic electromechanics : there is no garantee of a break-before-make on the data output and there are good chances of transient short circuits.

The original MUX tree approach garantees that there is no contact between the Vcc and 0V. Paralleled relays create the corner case where one switches some data that is 0V while another relays is still switching Vcc.

One solution is to add protection resistors on Vcc and 0V. This resistor is needed anyway futher down the signal path.

The other solution is to work with a different logic level : only 0V is switched, otherwise left dangling. This becomes a large "wired-or" network (à la TTL and open collector). No risk of shorts but the level must be restored so a "buffer" stage is required, drawing 1 relay power unit, added to the already constant unit to select one register. The load is pretty constant now, instead of jumping from 0 to 3 all the time. Which approach is better, since the averages are equivalent again ?

Another concern is the latency of the control signal tree: 2 relays-times, with potentially small discrepancies between different branches. Driving 16 relays at once is quite a challenge, no ?

Each coil uses a bit more than 2V so at least 36V is required but standard voltages 24V and 48V are easier to find. I want to avoid high voltages, by the way, and I have some 24V units. 8 coils will need about 20V, which can be obtained by under-volting the PSU (with the tuning pot).

The relays are rated for 100V and 100mA: 2 paralllel strings of 8 coils will draw at least 120mA so an additional 20mA must be drained (through a resistor).

In the log Pre-Biased, or Hysteresis Relay Logic, I see that some, but few, relays require about 60mA, 20% more than the others. These could be "binned" before assembly to save a bit of energy. I'll probably have to build a custom version of @matseng's #ReTest - Relay timing tester