At first sight, parallel digital I/O seems simple and straightforward. You make a board with 40 lines of I/O and cable it to a 40-channel signal conditioning board. Some people needed more, and that doubles the boards and cabling. One can try making an 80-channel board, the SPIBB80.
At this point I thought this was a lot of connector pins and cable and bandwidth, given that the STEbus can only change one byte at a time. Surely it would be more economical and space-saving to have a multiplexed bus, and have that done by the signal-conditioning boards. Just four address bits would select 16x8 = 128 bits, using 4 extra wires instead of 120.
It would need 16 output latches, but that would be no more expensive than 16 output ports driving a wide ribbon cable at the source.
Another point is that the 8255 ports are buffered by 8-bit LS245 chips. Their direction can be set, but all the bits in a port have to have the same direction. Having lost much of the flexibility of the 8255, you might as well just have a TTL chip for an output port and discard the 8255. The SPIBB80 does this, and adds a useful timer chip.
I'm uploading this board as a project because I am considering using it as an IDE controller. There are several 8255-to-IDE project designs on the web. Adapting an 8255 board to do the job would save a great deal of time writing driver code.