This project is about developing an easy-to-use high-level hardware development tool, and an FPGA board to use it on.
Handel-C is a language related to C and Occam, designed for the purpose of translating programs directly into hardware. Handel-C was available and in use about 10-20 years ago, I'm not sure whether anybody still uses it now. Originially developed and sold by Celoxica, the DK Design Suite product which includes an implementation of Handel-C has since been aquired by Mentor Graphics.
Although Handel-C allowed more-or-less direct compilation of ANSI-C programs to hardware circuits, the resulting circuits were seldom very good. More usually, Handel-C and the associated IDE served as a rapid development language and environment, in which a programmer could directly write parallelised, pipelined Handel-C programs which would result in a reasonably efficient circuit. It was also possible to use it to gradually refine an ANSI-C program into a form more suitable for hardware implemention.
The subset of Handel-C that I am working on is called 'Small-HC'. It supports some of the features of Handel-C, and more will be added over time. The following features are currently supported:
A short example program for flashing an LED (very quickly) is shown below:
unsigned 1 testbit;
port output(testbit) (163); // 163 is the output pin number on the FPGA
testbit = 0;
testbit = 1;
The starting point for this project will be a compiler for a subset of the Handel-C language. I want to target Lattice iCE40 FPGAs, because the bitstream for these devices has been reverse engineered, and open source place and route tools are available. (See project IceStorm).
This compiler is based on the same research into hardware compilation that Handel-C was based on. One of the key papers can be found here: Compiling occam into FPGAs
Initially my Handel-C subset compiler will be modified to produce verilog output (it was originally written to produce VHDL suitable for Atmel AT40K FPGAs), which can be fed into the IceStorm tools. Later, the compiler will produce a netlist, and I’ll write my own tools to map and place-and-route for the iCE40 architecture.