Homebrew CP/M-computer powered by Arduino Nano

My homebrew Arduino Nano-based CP/M computer in action (recording with TV tuner):

• power on
• memory test
• CP/M loading
• DIR command
• virtual screens toggle
• CPU test
• BASIC

8080/8085 CPU Exerciser from Ian Bartholomew & Frank Cringles successfully completed (screenshot from TV tuner):

Video output unit based on Arduino Nano + 23K256 in action - per-pixel (smooth) and character-by-character (step) scrolling up and down (the signal is recorded with a TV tuner.):   

A similar approach (Roller RAM) was used in 8-bit Amstrad computers.

I started a companion project to expand the graphics capabilities of my "nanocomputer". Another Arduino Nano acts as a video card that provides a monochrome image output on TV with a resolution of 320 x 244 (like the Sega Genesis, 240p format)! And this is not drawing lines in the demo format, this is a module with  pixel video memory - I use SPI RAM 23K256 as it. As a basic option, I want to make time-divided access to this chip - during 244 active pixel lines, the video processor owns it, and the remaining 68 lines - the memory can be used by the main processor. Well, now I just for "proof-of-concept" implemented control via UART. This is the picture my video card gives out after loading via UART into video memory - I converted a screenshot from the FoxyLand game for Sega Genesis to monochrome - the picture was taken using a TV tuner (I dug up my old 609 Beholder in the bins):

I added video recorded from CRT screen:

Boot screen on CRT TV:
https://acdc.foxylab.com/sites/default/files/cpm4nano_boot_crt.jpg

Added indication of access to the I2C bus (in fact, access to FRAM) - an LED that lights up when the SCL line is low. The quick-and-dirty approach to connect the LED through a 2 kOhm resistor did not pass at all - there was not a single memory module on the bus - it turned out to be too strong pull-up, although it worked after 4.7 kOhm, but in 7407 there are free pins, so through this buffer it turned out more reliable.

Now the RAM "module" schematic looks like this:

I did a redesign of the project, now it looks like this:

Evaluated the influence of the size of the instruction cache on the real speed of the "nanocomputer" operation using the example of the speed of thinking the first move by the machine in MICROCHESS (results for the TURBO mode, the video image was not drawn):

• without cache - 291 seconds;
• 4-byte cache (too small, overhead does not pay off and degrade speed) - 580 seconds;
• cache 8 bytes (optimum) - 21 seconds !!!;
• cache 16 bytes (too large, the overhead does not pay off) - 26 seconds.

A companion project has begun - an i8080-based system emulator on Rust - me select from the list of binary files in the program directory the desired one (for example, BASIC, Minol or chess) and run:

The emulator successfully passed the famous "exerciser" test: