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68K CPU with Frame Buffer on FPGA

Working with AMR's build and improvements to the TG68 FPGA project

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I recently completed a build of Jeff Tranter's build of the TS2 68000 CPU. It turned out pretty nicely but has serious limitations due to the original memory map of the TS2 which only had 32KB of SRAM from 0x000000-0x007FFF. The PROM is located in the next 32KB space from 0x008000 to 0x00BFFF. Porting the assembly language Tutor ROM code to higher memory proved to be quite painful. 

A Better Target Design

A helpful person in the MOTOROLA 68000 / 68K ASSEMBLY LANGUAGE PROGRAMMING Facebook group pointed me to AMR's TG68 Experiments pages. 

One of the advantages is that this design uses the 32MB SDRAM on typical FPGA cards. 

I made a build of AMR's design targeted to Cyclone IV and V FPGA cards and documented it in a log of the TS2 build (SDRAM Working in a Different Context). In particular, this leverages from Part 14 of the series. If you want to try AMR's project, start with the Master branch here.

The project creates a very powerful 68000 FPGA project and has a good narrative of the progress AMR made in the work but is short on details. Many of these details require digging into AMR's source code. I should note that I opened an issue on his Github page and he was very helpful.

This project will try and fill in some of the gaps in AMRs documentation. 

  • Fixed Display RAM Accesses

    land-boards.com3 days ago 0 comments

    The rectangles code wasn't working correctly on the EP4 FPGA card. Luckily, I found the problem relatively easily. Required setting the rows and columns for the SDRAM part that is used on the card. In the C4BoardTopLevel file.

    tg68tst : entity work.VirtualToplevel
      generic map (
        -- W9825C6KH-6 Winbond 4M X 4 Banks x 16 bits SDRAM
        -- 13 rows, 9 columns
        sdram_rows => 13,
        sdram_cols => 9,
    

     The same fix needs to be done for the Cyclone V card since it used the same SDRAM part.

  • Bootloader and SD Card

    land-boards.com4 days ago 0 comments

    Boot Process

    When AMR code runs it loads the executable program via a bootloader from the SD card. The bootloader code runs from ROM on the FPGA.

    SD Card Image

    The SD Card contains a single image, boot.sre . This image is loaded by the bootkiader when the card is powered on (or reset) and run automatically.

    The image is an S record.

  • GitHub under VirtualBox

    land-boards.com4 days ago 0 comments

    Sync up with repository

    git pull

    Move changes to GitHub

    git add .

    git commit 'stuff'

    git push

  • Build on EP4CE15

    land-boards.com4 days ago 0 comments

    Uses a bit more resources on an EP4CE15 card:

  • Software Build Toolchain

    land-boards.com09/07/2020 at 16:20 0 comments

    Assembler

    • vasm - Assembler
    • Built from source on Linux.

    C Compiler

    • GCC - 68k Cross-compiler
    • Built from source on Linux

    Build environment

    • Run in VirtualBox under Windows.

    Example Software

    Makefile for Rectangles code

    ARCH    = 68000
    BASE    = /opt/m68k-elf/bin/m68k-elf
    CC      = $(BASE)-gcc
    LD      = $(BASE)-gcc
    AS      = $(BASE)-as
    CP      = $(BASE)-objcopy
    DUMP    = $(BASE)-objdump
    VASM    = ../../../vasm/vasmm68k_mot
    
    # we use crt0.s from here
    STARTUP_DIR = ../../Firmware_Common
    COMMON_DIR = ../../Firmware_Common
    
    BUILD_DIR=m68k_obj
    
    STARTUP_SRC = $(STARTUP_DIR)/startup_app.s  $(STARTUP_DIR)/premain.s
    STARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(STARTUP_SRC))
    
    COMMON_SRC = vga.c uart.c interrupts.c
    COMMON_OBJ = $(patsubst %.c,$(BUILD_DIR)/%.o,$(COMMON_SRC))
    
    MAIN_PRJ = Rectangles
    MAIN_C_SRC = rectangles.c
    MAIN_C_OBJ = $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_C_SRC))
    
    MAIN_S_SRC = draw.s
    MAIN_S_OBJ = $(patsubst %.s,$(BUILD_DIR)/%.o,$(MAIN_S_SRC))
    
    MAIN_OBJ = $(COMMON_OBJ) $(MAIN_C_OBJ) $(MAIN_S_OBJ)
    
    LINKMAP  = $(STARTUP_DIR)/ldscript_app.ld
    
    
    # Commandline options for each tool.
    
    CFLAGS  = -m$(ARCH) -I. -c -O6 -DDISABLE_UART_RX -I$(COMMON_DIR)
    
    LFLAGS  = -m$(ARCH) -nostartfiles -Wl,--relax -O6
    
    
    # Our target.
    all: $(BUILD_DIR) $(MAIN_PRJ).sre $(MAIN_PRJ).rpt
    
    clean:
        rm -f $(BUILD_DIR)/*.o *.elf *.sre *.rpt *.map *.lst *.srec *~ */*.o *.bin
    
    
    # Convert ELF binary to bin file.
    %.sre: %.elf
        $(CP) -O srec $< $@
    
    %.rpt: %.elf
        echo >$@ -n "End of code:\t"
        $(DUMP) -x $< | grep >>$@ _romend
        echo >>$@ -n "Start of BSS:\t"
        $(DUMP) -x $< | grep  >>$@ __bss_start__
        echo >>$@ -n "End of BSS:\t"
        $(DUMP) -x $< | grep >>$@ __bss_end__
        cat $@
    
    # Link - this produces an ELF binary.
    
    $(MAIN_PRJ).elf: $(STARTUP_OBJ) $(MAIN_OBJ)
        $(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
    
    $(BUILD_DIR)/%.o: %.c Makefile
        $(CC) $(CFLAGS)  -o $@ -c $<
    
    $(BUILD_DIR)/%.o: $(COMMON_DIR)/%.c Makefile
        $(CC) $(CFLAGS)  -o $@ -c $<
    
    $(BUILD_DIR)/%.o: %.s
        $(VASM) -Felf -o $@ $<
    
    $(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
        $(VASM) -Felf -o $@ $<
    
    $(BUILD_DIR):
        mkdir $(BUILD_DIR)
    

  • Software Examples

    land-boards.com09/06/2020 at 21:17 0 comments

    Code

    AMR has several code examples. I've added some documentation and comments to the code. If you try them, make sure you are on the master branch of AMR's code. I've also got the code in my Linux repo.

    HelloWorld

    Prints out strings and numbers on the UART serial port using printf.

    Rectangles

    I added these comments to the source code

    // rectangles.c - Draws rectangles on the VGA screen
    // random size rectangles
    // combined with previous rectangle colors
    // scrolls screen vertically as well
    // scrolls on vert sync interrupt
    // very busy screen
    // bootloader leaves debug window up

    FrameBufferTest

    Graphics test with sprite under PS/2 mouse control.

  • TG68 Hardware

    land-boards.com09/06/2020 at 14:04 0 comments

    This project is intended to be a software project but a description of the hardware is necessary as a reference to understand the resources available to the software.

    Features

    • Runs on Altera Cyclone IV and V FPGA Cards
    • 68000 CPU
    • 32 MB SDRAM
    • Host Serial Connection (USB to Serial) 
    • Video Display Unit (VDU)
      • VGA
      • PS/2 keyboard

    FPGA Cards

    Flow Status    Successful - Sun Sep 06 12:05:04 2020
    Quartus Prime Version    20.1.0 Build 711 06/05/2020 SJ Lite Edition
    Revision Name            SOC
    Top-level Entity Name    C5BoardToplevel
    Family                   Cyclone IV E
    Device                   EP4CE15F23C8
    Timing Models            Final
    Total logic elements     7,984 / 15,408 ( 52 % )
    Total registers          3629
    Total pins               134 / 344 ( 39 % )
    Total virtual pins       0
    Total memory bits        107,520 / 516,096 ( 21 % )
    Embedded Mult 9-bit els  2 / 112 ( 2 % )
    Total PLLs               1 / 4 ( 25 % )

    TG 68000 Core

    • 100 MHz?
    • Wait states
    • 32-bits of addresses connected?

    32MB SDRAM

    Host Serial Interface

    • FT-230XS USB to Serial
      • 115200,N,8,1
    • USB B connector

    Video Display Unit

    • VGA
    • PS/2 keyboard and Mouse

    Memory Map

    • 0x00000000-0x0000FFFF = ROM
    • 0x00100000 - Framebuffer
    • 0x0FFFFA -  Variables
    • 0x7FFFFE - The initial stack pointer
    • 0x800000 = VGA controller
      • Screen base address register
    • 0x810000 = Peripherals
      • Four counters, t0 through t3
      • 0x810010-0x810016 = Divisor register for all four counters
      • 0x81000e = Control word at which contains interrupt enable bits and status bits for counters t1 through t3.  
      • T0 acts as a prescalar for the other three timers, so with the system clock set to 112.5MHz, setting T0’s divisor to 1125 gives the other three timers a 100KHz base clock.
    • 0x820000 = Audio controller

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