I'm no expert in this, but was interested to learn more, so did some research and had a go at putting a circuit together. See the videos below for the research and building of the circuit, and this three-minute summary for a quick view of it:
How it works
The module currently provides three words (rows) of four bits (columns) each. Each row has a "row select" input; when it's high, that row is selected and its contents appear on the data bus pins, shown with green LEDs in the video. At the same time, the column amplifiers reinforce the stored data in the DRAM cells, so reading a row also refreshes it.
If a row is selected and something relatively low-impedance drives some of the data lines high or low, then the newly driven values will get written into the corresponding DRAM cells. There's no explicit read/write enable input.
It works pretty well at manual speeds. I'm planning to expand it to more words and more bits per word, and hook it up to a 6502 or Arduino to see what happens at faster speeds.
Here's a link to the circuit diagram, also in the gallery: https://hackaday.io/project/175774/gallery#b4bdff73509e92bea2cbd55bb8642105
And here are the videos in which I described my research, and built the first prototype.
Very many thanks for posting your work here, I love it.
I'm interested in building a minimal computer out of discrete components, one that is easily understood. RAM dominates the component count so DRAM becomes necessary to keep things small enough so that I may eventually finish.
My last design is at https://hackaday.io/project/19386-the-blinking-computer/log/158857-yet-another-memory-cell-2t but it's not very well written up I'm afraid. The main idea is that a 2N7000 stores charge, either just because the gate has capacitance or assisted with an external capacitor (I've not iimplemented the external capacitor). So a 2N7000 will stay on or off if electically isolated, up to a few minutes and that was good enough for me at the time.
Where we differ is that I used a S8050 bipolar transistor to allow access to the capacative storage, where as you have two 2N7000 back to back.
I'm very inspired by your work. In particular, you don't have separate read and write data lines which simplifies things very much. I have been very attached to LEDs to show the status of every bit, but without these I see that you could have just one set of address line decodings, one transistor to gate the access and one capacitor for storage. That's as minimal as it could ever get and there is a lot of beaty in that.
Thanks again for your work, it's inspied me to dust things off and play around again.