The RAM chips I have are NEC uPD424400-70. They are  1M x 4-bit FPM DRAM chips. The package is 26-pin SOJ.

Apple IIgs is a 16-bit computer. The processor is 65C816 and its data bus is 8-bit wide.  The RAM card is 4MB in size. The memory is divided to 4 rows. Each row is 1M x 8-bit . So, each row consists of two RAM chips. There are totally 8 RAM chips.

The computer has a memory expansion slot. It provides all the required control signals to interface the computer to DRAM chips. The computer also handles the DRAM refresh. So, the design of the RAM card is quite simple.

Design Goals

  • Small size. To reduce the cost of PCB
  • All supporting circuit is integrated to one GAL22V10 PLD

Memory Expansion Slot Signals

Here is the description of the expansion slot of signals

FRA0-FRA910 bit multiplexed RAM address. Connect to address bus of DRAM chips directly
CROW0, 12 bits select 1 of 4 RAM rows
/CRASRow address strobe for DRAM
/CCASColumn address strobe for DRAM
FR/WWrite enable to RAM.  This signal requires additional handling. See details below
D0-D7Data bus. Connect to I/O of RAM chips directly
/CSELSignals goes high when reading from RAM. The signal is inverted and then connected to /OE of RAM chips.
MSIZETell the computer the row size. = High for 256k, = Low for 1M. It is connected to ground.
14M, PH2CLK, A10-A15Not used by the RAM card

/CRAS and /CCAS Demultiplexing

The /CRAS and /CCAS signals must be demultiplexed to separate /RAS and /CAS for each row. It can be done by 74F139 IC.

FR/W Signal

The FR/W signal cannot be connected to DRAM /WE directly.  Here is the problem

During normal read/write operation, the /RAS signal goes active (low) first. Then, /CAS signal goes active. During DRAM refresh cycle, it is the other way round. The /CAS goes active before /RAS. It is call /CAS before /RAS Refresh. But 4M-bit RAM chip has one additional requirement. The /WE must switch to high before /RAS goes active. But FR/W signal provided by IIgs does not follow this specification. The state of FR/W is undetermined during refresh cycle. So, additional circuit is needed to detect refresh cycle and set /WE to high.

DRAM Refresh Detector

The first thing we need is a circuit to detect the refresh cycle. Here is the timing diagram.

The idea is to use a transparent latch.  /CRAS is the latch input. /CCAS is the trigger.  When /CCAS is high, the output of the latch equals to input. When /CCAS switches from high to low, the input is latched. During normal read/write operation, /CRAS is low when /CCAS switches from high to low. But during refresh cycle, /CRAS is high when /CCAS switches to low. When /CCAS returns to high, the latch is released.

Here is the first version of the circuit. During refresh cycle, the latch output is high and /WE is set to high.

Version 2

If version 1 is implemented with GAL22V10, it needs two output pins. So, I tried to further simplify the circuit. 

During normal operation, the FR/W signal is already valid before the latch is triggered. So, the circuit can be changed to this.

A transparent latch can be built from a multiplexer (MUX). And a multiplexer can be built from logic gates. So, the circuit becomes

The circuit is further simplified to:

This is the final version and it is implemented in GAL22V10.


I used WinCUPL to compile the logic of GAL22V10 PLD. The software can be downloaded from Atmel website for free. The software is very buggy and it crashes all the time. But it can do the job.  The programmer I used is Genius G540

PCB Design

SJ1 Jumper

It is a 3-pin jumper. If pin 1 and 2 are connected together. The RAM /OE signal is connected to and controlled by GAL. If pin 2 and 3 are connected, it is tied to ground.  When I designed the PCB, I was not sure that the refresh detection circuit would work. So, I added this jumper...

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