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General bit layout for instruction types

A project log for Instruction Set for ECM-16/TTL homebrew cpu

All the instructions lead out in systematic manner

PavelPavel 01/26/2022 at 10:360 Comments

All instructions are 16-bit wide (1 word), with optional extension of 16 more bits for immediate value needed for some of these instructions.

Bit patterns for the instruction types:

bits in instruction word:   FEDC BA98 7654 3210  [extension]
ALU:                        1xxx xxxx xxxx xxxx
Load/Store via Mem Pointer: 011x xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
Load/Store via direct addr: 010x xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
MOV:                        0011 xxxx xxxx xxxx
Load immediate value:       0010 xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
Jumps:                      0001 xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
Address Arithmetic:         0000 1xxx xxxx xxxx  xxxx xxxx xxxx xxxx
Miscellaneous ops:          0000 0xxx xxxx xxxx

All the 'x' places above can be either 0 or 1, depending on particular instruction.

The extension word with immediate value is always present for Loads/Stores via direct address and Loads of immediate values, while for the Loads/Stores via Memory Pointer + offset, Jumps and Address Arithmetic instruction types it is optional, and depends on particular instruction. Thus, although I tried to make the ISA RISC-like, it has some elements of CISC in a sense that not all instructions are the same size.

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