All instructions are 16-bit wide (1 word), with optional extension of 16 more bits for immediate value needed for some of these instructions.

For description of each major type, follow the link from this list:

Bit patterns for the instruction types:

bits in instruction word:   FEDC BA98 7654 3210  [extension]
ALU:                        1xxx xxxx xxxx xxxx
Load/Store via Mem Pointer: 011x xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
Load/Store via direct addr: 010x xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
Load immediate value:       0011 xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
MOV:                        0010 xxxx xxxx xxxx
Jumps:                      0001 xxxx xxxx xxxx  xxxx xxxx xxxx xxxx
Address Arithmetic:         0000 1xxx xxxx xxxx  xxxx xxxx xxxx xxxx
Miscellaneous ops:          0000 0xxx xxxx xxxx

All the 'x' places above can be either 0 or 1, depending on particular instruction.

The diagram showing bit layouts:

For some instruction types, there are several sub-types, especially for the ALU instructions.

Instruction types are color coded according to opcode, which ranges from 1 to 5 bits.

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The extension word with immediate value is always present for Loads/Stores via direct address, Loads of immediate values and Far Jumps, while for the Loads/Stores via Memory Pointer + offset and Address Arithmetic instruction types it is optional, and depends on particular instruction. Thus, although I tried to make the ISA RISC-like, it has some elements of CISC in a sense that not all instructions are the same size.