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Homebrew 16 bit relay computer

Goal of the project is to develop and build a homebrew 16 bit relay computer

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The new relay system is a classical Accu CPU like some CPUs of the good old 80s. The system was simulated using the game "Logic World", now the real world build has startet! If you want more information: you find the link to the project homepage on the left. And the complete circuit diagram in the download area. Just for fun.

Overview

The system ist a very simple CPU using an Accu register like CPUs in the 80s.  All mathematical operations are using the Accu, also all store / load operations. And, because it is a "High Performance" relay system, the program counter has its own adder which is only able to add 1 to the program counter.

Here you see an actual picture of the complete system:

The following diagram shows the logical structure of the 16 bit relay CPU. It was built around an accumulator. A special feature is that the program counter has its own +1 adder. There is also a register that can store a return address, enabling one level of subroutine support.

Note: The PC_HR register is necessary, because I can not write the changed PC based on its own value plus 1 direct into the PC...

One detail is important to understand the design of the system: all registers, which are realized by "self retaining" relays, have to be cleared before any information can be stored, also before the stored information can be changed. Thats the reason why the clock of the system is not an ordinary clock as you know it from digital systems. The clock of this system consists of 4 different pulses:

The following table shows the command set of the CPU:

The CPU is able to adress the memory using 3 different adressing modes. a) LD X is loading the Accu with the dataword stored in the adress after the opcode, b) LD M(X) is loading the Accu with the data stored in the memory adress stored after the opcode, and c) LD M(M(X)) is ... yes, indirect adressing. The dataword after the opcode contains the adress where the CPU finds the adress of the dataword that will be stored in the Accu. Is adressing mode c) really necessary? Maybe not. But it makes it easier.

And, as you can see, a CALL / RET set of operations is also avaliable. No, there is no stack realized, only one subroutine level is possible. The return adress is stored in the register SR.

And now you see some pictures of the different module boards. The first one here is the control board:

The following board is responsible for address calculation:

Here you can see the complete ALU, the accumulator register, and the branch logic. The green PCBs make up the 16-bit ALU, while the small boards at the bottom implement both the branch and carry logic.

Here is the input/output decoder, the 16-bit output register, and the contactor, which switches a lamp (this was used for the 1 Hertz challenge):

At the very bottom, we find the memory implemented using an Arduino, as well as the clock generator, which is also built with a separate Arduino.

The Simulation using "Logic World"

The following images show the Simulation of the complete system in the game "Logic World". This simulation was used to design the system and to check different design variants.

The relay element:


System overview:

Circuit diagram

The complete system circuit diagram is avaliable in the download section.

The software simulation:

To check if the command set of the CPU is useful, a software simulation using an Excel macro was developed. Using this macro it is possible to step through the code, watch registers and memory and to go forward until a breakpoint. The following picture shows the simulation with an program which multiplies two numbers using shift operations.

RelCPUMathCoprocessor.zip

FPGA acting as a mathematical coprocessor

x-zip-compressed - 7.46 kB - 12/25/2025 at 10:08

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Testprotokoll RelaisKondensator small 20250913.pdf

Measured Relay Timing

Adobe Portable Document Format - 1.92 MB - 09/19/2025 at 09:10

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ArduinoLoopSmall.pdf

Measured Arduino Loop

Adobe Portable Document Format - 196.38 kB - 09/19/2025 at 09:09

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WriteSignalSmall.pdf

Test of Write Signal

Adobe Portable Document Format - 697.55 kB - 09/19/2025 at 09:09

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ReadSignalSmall.pdf

Test of Read Signal

Adobe Portable Document Format - 1.91 MB - 09/19/2025 at 09:08

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  • 1 × 24V Relay
  • 1 × Diode

  • Release of a new video

    Peter2 days ago 0 comments

    In this video, I’ll explain the design of the adder in my relay CPU. Even though relays are generally very slow, this adder is much faster than you might think. There is one key advantage I describe in the video.

  • Relay CPU using an FPGA as mathematical coprocessor

    Peter12/25/2025 at 10:39 0 comments

    In the following video, the relay system calculates the square root of 60,000 with an FPGA acting as a mathematical coprocessor. The VHDL code running on the FPGA emulates the relay system’s design, so the square-root routine is identical to the one shown in the video from a few months ago.

  • Finished 16 input ports

    Peter12/19/2025 at 05:44 0 comments

    Because I had to realize that using the output ports as inputs works at first glance, but causes problems on closer inspection (clearing the output register is no longer possible, because an active input may keep the holding voltage at “1”), I built a 16-port input register instead—essentially just relay-implemented switched inputs onto the data bus.

  • New FPGA board

    Peter12/02/2025 at 21:05 0 comments

    The new FPGA board is finished and now simulates a VHDL-based variant of the relay CPU. The large PCB serves as the interface to the 24 V relay system, and communication takes place via the system’s 16-bit I/O register.

    In a first communication test, we sent an integer to the FPGA and successfully received the value multiplied by two

  • FPGA Core calculates square root

    Peter11/17/2025 at 07:01 2 comments

    The following picture shows the result of calculating the integer square root of 60,000: 244 (1111 0100 in binary), computed by a relay CPU core implemented in an FPGA. The program running on the FPGA is the same as the one used on the relay CPU.

    The FPGA will now be connected to the I/O register of the relay system and used as a mathematical coprocessor.

  • Relay CPU writes calculation result to display

    Peter11/09/2025 at 15:00 0 comments

    The relay CPU calculates 156 * 67 and writes the result (=0x28D4) to the display:

  • Relay CPU reacts on user input

    Peter11/02/2025 at 10:03 0 comments

    The 16 bit output register is also able to act as an input register:

  • Found a second defect relay

    Peter10/27/2025 at 08:57 0 comments

    The following video shows how I found a second defect relay in the relay CPU:

  • Bugfixing a defect relay

    Peter10/05/2025 at 15:00 0 comments

    The following video shows how I found, analyzed and repaired a defect relay in the system

  • ALU speed test

    Peter09/26/2025 at 16:10 0 comments

    The following video shows the ALU speed test...with a perfect result

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Discussions

Paul McClay wrote 12/25/2025 at 19:39 point

Does "...actual picture of the complete system" mean... finished? Merry Christmas to you!

  Are you sure? yes | no

Peter wrote 12/25/2025 at 20:12 point

Hello — no… I think the project will never really be “finished.” There are still a few ideas for extensions/improvements. And Merry Christmas to all of you.

  Are you sure? yes | no

Paul McClay wrote 12/26/2025 at 16:39 point

Thinking of a few ideas for extensions and improvements sounds a lot like the basic machine is basically done. Congrats!

  Are you sure? yes | no

Tom Goff wrote 10/02/2024 at 17:49 point

Great work! Konrad Zuse would be impressed with your hard work.

  Are you sure? yes | no

Peter wrote 10/02/2024 at 20:08 point

Thanks a lot...and today I uploaded a new video, the system is now able to multiply.

  Are you sure? yes | no

Ken Yap wrote 02/25/2024 at 23:44 point

👍 I commend you on your persistence with this epic project. I'm sure it will be a classic work when it's done. Looking forward to seeing that.

  Are you sure? yes | no

Peter wrote 02/28/2024 at 20:43 point

Thanks for your encouraging words. My plan is to be finished at the end of 2024...we will see.

  Are you sure? yes | no

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