Gigatron TTL microcomputer

Just because! A home computer without microprocessor

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In 1975 Wozniak famously designed the Breakout arcade game out of 44 simple chips, without using a microprocessor, simply because those weren't available to him at the time. When one year later the MOS 6502 and Zilog Z80 were launched, his Apple 1 started the microcomputer revolution. The debate still rages about which processor was the better one. But more interesting is to investigate if these devices were really necessary for the personal computer revolution at all: what would have happened had they never appeared?

Update: For info on the kit version of this project, check out:

History followed one path
There were many other ways
It will always be like that

Can fewer than 40 old-skool TTL chips implement a multi-megahertz microcomputer with video and sound?

This project started as an exploration of what you can build from 30-40 simple logic chips. It has turned into a general purpose 8-bit microcomputer without any microprocessor driving it. I initially designed this on a large breadboard in early 2017, but soon after that I converted it all to a small PCB. It has VGA-compatible 60 Hz video in 64 colors and can display full-screen images, scroll them and play sound. Soon it will be running games like Pac Man and Space Invaders. But just for fun, I'll keep everything compatible with the breadboard design.

This is what we have now:
• 8-bits system built out of 1970s TTL chips (74LS)
• 34 TTL ICs, or 930 logic gates, for the CPU proper
• No microcontroller and no complex chips (such as the 74181 ALU)
• 16-bit virtual CPU runs ported versions of classic games, WozMon, BASIC, ...
• 8-bit virtual CPU runs 6502 programs without blinking an eye
• Only simple ICs, such as AND/OR, 4-bit adders, multiplexers, registers and so on
• 6.3 MHz. Can be pushed to 15 MHz with 74F logic and faster RAM
• 32kB 70ns RAM
• Harvard architecture with EPROM for kernel and cold storage
• Operates on 2.5W, or below 0.5W for the 74HCT version
• RISC with pipelining:  1 instructions per clock (sometimes 2...)
• Instruction decoding with diodes
• Nice instruction set: ADD/SUB/AND/OR/XOR, conditional jumps, many useful addressing modes
• 60Hz 64 color VGA and 4 sound channels bit-banged from software
• Originally designed and built on a solderless breadboard in 6 weeks (see the logs!)

The build has become a contradiction of itself. To reduce the parts count, every hardware function is essentially software-defined: video, audio and I/O are all handled by software. Video at the pixel level. Audio at the sample level, in 4 channels. Even the applications themselves are running in a non-existent 16-bit processor (aka interpreter).

Yet there is no microprocessor chip in there that runs the software of any of those virtual subsystems: it's all handled by the TTL circuit, acting as a minimalistic CPU and switching rapidly between these tasks. Not only does it work, the board is smaller and faster than the microcomputers of the day, including the first IBM PC. Having no microprocessor might have been better than having any of the time :-)

Check the videos for the current capabilities. The HaD blog section has the full story in all detail, so don't miss that if you're interested.

Some concepts to ponder about before starting

  1. How many bits? 4, 8, 16, 32, ...
  2. Software-generated video or hardwired?
  3. Harvard or Von Neumann architecture?
  4. Single cycle or multi cycle? Pipelining?
  5. ALU chips or not?
  6. Sliced ALU or full width?

A rule of thumb is that a minimalistic four bit system can be done in 10 chips, an eight bitter needs no more than 20 chips and going to 16 bits roughly doubles that again. Not all units double in chip count, but by extending the buses you will also have need for more addressing modes for it all to make sense. For example, a four bitter might work fine with a 256 word memory and absolute addressing, but with larger memories you'll need ways to construct addresses dynamically. Also, add more chips if extra functionality is required, such as high speed, a stack pointer, interrupts, a custom ALU or video.

Simplest possible concept

One concept, probably the simplest, is to replace the TrinketPro from the earlier breadboard VGA from TTL and SRAM with a minimalistic 4-bit TTL CPU. We will then get a working system with around 25 chips, or about 30 if we make a custom ALU. It will...

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2019 Vintage Computer Festival Berlin presentation

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2019 Hackaday Unconference UK slides

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The Effect of R17.pdf

Measuring across R17 (68Ω)

Adobe Portable Document Format - 3.65 MB - 02/12/2019 at 11:37



2018 Vintage Computer Festival Zürich presentation

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Cycle exact Gigatron emulator and ROM v3 for Hackaday Superconference 2018 badge (hex file and modified sources)

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View all 11 files

  • Heatmap of Gigatron applications

    Marcel van Kervinck7 days ago 0 comments

    A static RAM map constructed by overlaying all GT1 files in the GitHub repo.

  • The anthem of 8-bit computing

    Marcel van Kervinck08/13/2019 at 10:07 0 comments

    A bunch of TTL chips playing the "anthem of 8-bit computing". Four channels: 2x pulse, 1x triangle, 1x noise

    The player is an enhanced version of the Contrib/at67/midi player in the gigatron-rom repository. The noise is created from waveform 0 ("metallic") that receives a randomised XOR modulation 60 times per second.

    Only 7400 logic. No microprocessor, no video chip, no sound chip.

    The Arduino is used to load the music and player into RAM. You see that happen in the first few seconds of the video.

  • Microchess and becoming an Apple-1

    Marcel van Kervinck06/23/2019 at 19:54 0 comments

    Today my Gigatron believes it's an Apple-1 instead of a TTL computer. It's running the original 6502 wozmon code with mockup terminal I/O patched to it. Of course the patching, and some relocation, make up for the system differences. With a tongue in the cheek, we can say it turns the Gigatron into an Apple-1 clone!(*)

    Here we can see the "Apple-1 on TTL" running MicroChess code for the first time, with kudos to @oscarv for helping out.

    (*) After all: "Apple1 = 6502 + RAM + WozMon ROM + PIA", and "PIA = DSP + KBD". There wasn't more to it and we emulate it all!

    In reality, any original Apple-1 software will likely need some relocation and a tiny bit of patching for I/O. More technical details in the user forum:

  • Adding 6502 support

    Marcel van Kervinck06/13/2019 at 00:15 5 comments

    The computer without microprocessor is becoming dual core.

    Today it ran its first 6502 program.

    All of the 6502 addressing modes are implemented, and a fair amount of instructions as well. The v6502 interpreter runs in place of the standard 16-bits application vCPU. Switching between the two virtual processors vCPU and v6502 is a matter of modifying a zero page variable. The video driver dispatches at the next available scan line, so very lightweight.

    The impressive thing about the 476-byte Baum-Wozniak 6502 disassembler isn't just its size: it's that it seems to be secretly designed for 26 character wide displays. Now that's quite a foresight by these gentlemen! Here you see it running on the Gigatron, disassembling it's own code:

    More details on the user forum:

  • Having fun with electron beam lithography

    Marcel van Kervinck11/15/2018 at 11:15 2 comments

    The joy of using hypermodern multiple e-beam direct-write lithography to "advertise" TTL technology from the 1960s... This is an electron microscope image of the Gigatron startup screen. This time it isn't displayed on a VGA monitor (or on a supercon badge), but printed on a silicon test wafer as used for IC making. The image was printed using a Mapper FLX-1200 e-beam writer. For comparison, a human hair is typically 75 µm in thickness.

    The Mapper principle is much like that of an ink jet printer head with hundreds of nozzles, except we're using accelerated electrons here instead of ink, and silicon wafers instead of paper (and there are no colors). The beams each have a spot size of under 30 nm and they're scanning the surface with a positioning accuracy of below 3 nm. They're all perfectly stitched together to seamlessly cover the large area needed to make complex devices. The wafer was coated with a thin layer of resist material, and everywhere a sufficient number of electrons landed, an image formed that could be developed. 

    This tiny area of 24 µm x 18 µm shown above was printed in just a few milliseconds by a couple of hundred parallel and independently controlled electron beams, all focussed on the wafer in a high-vacuum chamber. This image is a small part of a much larger test pattern. The resolution is in the 40-50 nm range here. The e-beam writer has tens of thousands of beams all working in parallel. The data stream to support that is about 3 Tbit/second and is generated by a large rack filled with FPGAs.

    A SEM is needed to view the result because the details are too small for optical microscopes. This super fast e-beam technology is developed to make new types of security ICs possible, but it has other applications in nano-fabrication as well (one is entertaining the engineers working with it).

    The image contains a schematic of the iconic 7400 quad NAND chip, introduced in the late 1960s. An actual NAND gate, or even a single transistor from the day, would be much larger than this entire image. The typical line widths in those early days of IC manufacturing were in the order 10 µm.

    Courtesy Mapper Lithography and CEA Leti.

    [Edit 2019-02-11: Unfortunately, Mapper is no more. Looking for a job now! ]

  • More 8-Bit Goodness & Superconference

    Marcel van Kervinck10/30/2018 at 17:21 3 comments

    The 8-Bit Guy just published his review of Pluggy McPlugface, Tiny BASIC v2 and the new games in ROM v3. And oh... we'll show it at the Superconference this weekend!

    For those interested, I brought a very limited number of kits to Pasadena. They can go for a nice discount because I don't want to bring them back home.

    Update: The conference badge was screaming for this hack:

    The emulation is slow as molasses, running at 3 frames per second, instead of 60 frames. Contrary to my expectation, the slowdown doesn't come from the LCD update. Instead it's all due to the cycle-exact simulation which is based on the gtemu.c reference.

    Hex file and modified sources attached to the project. Game controller button [A] is mapped to the DEL button. The BKSP button takes over the role of [Select] for switching between video/speed modes. You don't see the different scan line effects, because the LCD always only displays the first out of every 4 VGA scan lines (even in "full mode", aka "mode 0"), with the odd LCD lines always black. The applications still run faster depending on the mode. Continuous presses don't work, you have to simulate them by repeating. I managed to play Racer that way. Typing in Tiny BASIC v2 goes remarkably well.

    Credits must go to @shaos, @jaromir and @rogerrandom for helping me plow through all the PIC stuff, as I never worked with any of that before.

  • Full circle

    Marcel van Kervinck09/16/2018 at 18:27 2 comments

    Today, a circle closed at the Centre for Computing History in Cambridge, UK.

    How? Well, one week before this project started here on Hackaday, I was at the Computer History Museum in Mountain View, US, and jokingly posted the following remark on Facebook:


    That's an original Apple-1. The Apple-1 next to the Gigatron is a beautifully done replica. It's fully functional, complete with cassette interface. The PCB is drawn in the same way and the chips even have 1970s date codes on them. It's on display in an operational state. I could play around and type commands in the original Woz Mon to verify that the Gigatron version works the same.

    Many thanks to David Williams for the great opportunity!

  • TTL is hot

    Marcel van Kervinck08/12/2018 at 16:27 0 comments

    One of my side projects is to convert a board to original TTL series where possible, or at least to 74LS series with the oldest chips I can find. The breadboard prototype was fully 74LS, the kit edition is 74HCT.

    At a local electronics shop I recently found quite a few ICs that were manufactured more than 43 years ago, in 1975. These are "new old stock": never used before and the pins still unbent. Some are indeed original TTL series as existed in the 1960s, not 74LS (Low-power Shottky) as introduced in 1971. They're plug-in compatible with the Gigatron design and the system works fine at full speed:

    Although it is cool, it also gets hot! Original TTL consumes an order of magnitude more power. Due to this so far I only "upgraded" to original TTL the upper half the logic unit, the X register, the memory address unit and the program counter. Those 14 chips, together with a few 74LS replacements as well, already increase the current to 740 mA, or about a ten-fold from the kit version. Above that the multi-fuse and MCP start to do their thing. Remember that USB safety is the reason the kit comes with much more power-efficient 74HCT components in the first place.

    The nice thing about the 7400-series is that improved series remained compatible in pin layout and voltage levels.

    • 1966: introduction of the original 7400 series
    • 1971: introduction of 74LS series
    • 1983: introduction of 74HC(T) series

    I have them all on a board now.  The difference in generations is clearly visible.  The old TTLs get up to 60 degree Celsius. The blue square isn't a cool oasis in the middle of a hot desert. It is a reflection on the gold plated ceramic lid of a vintage SRAM.

  • Back to BASICs

    Marcel van Kervinck07/24/2018 at 20:33 0 comments

    I almost forgot about the project's original objective that I had in mind when it started one and a half year ago: to build a circuit from TTL components that can play Tic-Tac-Toe on an LED matrix. So lets correct that: today, with minor adjustments, Tom Pittman's Tic-Tac-Toe from 1977 is running on the Gigatron :-) Source code in GitHub.

    Ok, the planned LED matrix has morphed into a video screen along the way. That's just feature creep.

  • 200+

    Marcel van Kervinck07/16/2018 at 08:17 1 comment

    We've recently celebrated a dream milestone: there are now more Gigatrons out there than Apple-1's ever produced!

View all 68 project logs

Enjoy this project?



Yann Guidon / YGDES wrote 09/26/2019 at 07:08 point

the Gigatron is mentioned at about 1:17 on the EEVblog !

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Marcel van Kervinck wrote 09/26/2019 at 07:41 point


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Stefano wrote 07/05/2019 at 15:08 point

First of all compliments for the idea and the nice realization! :)

I was very interestingly looking at the project, and among the things that might be improved for a newer version (e.g. clock frequency, keyboard instead of controller, cartdridge/expansion port, etc), I was thinking that instruction set might be a very relevant one.

The following proposal for a revisited instruction set should not change much the number of logic ports and the current schematics, but seems to me more rational and powerful.

Bit 5:7        Bit 2:4            Bit 0:1
Operation      Mode               Bus

0. LOAD        0. [D,X],AC        0. D 
1. AND         1. [Y,X],AC        1. RAM     
2. OR          2. [Y,D],AC        2. AC
3. XOR         3. [Y,X],(**)AC    3. IN
4. ADD         4. [D,X],Y              
5. SUB(*)      5. [Y,X++],AC                 
               6. [Y,D],X
               7. [Y,X++],OUT            

6. STORE       0. [D,X]           0. D
               1. tbd             1. tbd
               2. [Y,D]           2. AC
               3. [Y,X]           3. IN
               4. Y
               5. tbd
               6. X
               7. [Y,X++]

7. JUMP        0. jmp y,bus       0. D
               1. AC>0 (bgt bus)  1. [D]
               2. AC<0 (blt bus)  2. AC
               3. AC≠0 (bne bus)  3. IN
               4. AC=0 (beq bus)
               5. AC≥0 (bge bus)
               6. AC≤0 (ble bus)
               7. Branch always


(*) put A as second operand (meaning doing "minus A") because:
   - A minus D (fixed constant) can be always be transformed in an addition at compile time
   - the instruction will be also useful to negate A (as 0 minus A), and is already useful in conditional jumps calculations
   - for the addition first or second is the same

(**) add also carry on this combination if possible (it was redundant so it will be useful) and many instructions can be used to clear carry flag

With this set it will also be possible to reuse with very little changes all the current sw.

What do you think about it?

  Are you sure? yes | no

Marcel van Kervinck wrote 07/08/2019 at 22:52 point

Sorry I didn't see the message earlier. You would have to draw the control logic. This design is based on reducing the number of parts as much as possible (without crippling the capability of making software too much). As said in the log when we worked on this: the instruction set is the result of that process, not the beginning:

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Stefano wrote 07/10/2019 at 19:36 point

This proposal was to try to maintain a similar hw complexity as now (mostly rewiring or with some little change on the CU arrangment)! ... Anyway I got the point of reducing and I'm trying to work on this concept, trying to see if I can make some relevant proposal... let's see! :)

  Are you sure? yes | no

Marcel van Kervinck wrote 07/11/2019 at 14:06 point

It's difficult to judge without seeing the full proposal. We don't have flags now for example (as explained in the FAQ). But don't let that stop you. Just build your machine the way you believe is best, and share your results! The proof of the pudding is in the eating after all.

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Stefano wrote 07/12/2019 at 20:38 point

Yes, the absence of the carry is pretty relevant (for this reason I wrote if possible in the notes), but the rest should be quite easily doable. In the new design I'm anyway trying to keep the carry. Hope to serve in the medium term a nice pudding variation! :)

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Marcel van Kervinck wrote 06/10/2019 at 21:06 point

I started a thread on 6502 emulation here: I think I have the skeleton for an emulator that can be made to work.

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Jac Goudsmit wrote 11/21/2018 at 23:33 point

Ha, I just noticed the picture from your racing game has the Evoluon on it. Now I have to save up and buy it just for that :-)

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Marcel van Kervinck wrote 11/21/2018 at 23:36 point

Well spotted! I can put one aside and reserve it for you...

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Jac Goudsmit wrote 12/11/2018 at 22:46 point

My Gigatron kit just arrived in the mail. It's absolutely gorgeous, even better looking than on TV :-)

Great job, Marcel and Walter!

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Marcel van Kervinck wrote 10/30/2018 at 17:18 point

The 8-Bit Guy has just released an update video on the Gigatron \o/

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Ingo Truppel wrote 10/15/2018 at 11:56 point

I got into contact with Gigatron at the VCFB 2018. I could not resist to buy one. Thanks for the detailed explanation and nice presentation. I'm looking forward to build the Gigatron myself.

In between my Gigatron is alive:

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Marcel van Kervinck wrote 10/09/2018 at 20:16 point

Decided to attend Vintage Computer Festival Berlin next weekend. Looking forward !

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edsjac wrote 05/30/2018 at 20:52 point

Really nice and interesting project! Open source Hardware and Software. 

Many people can use it to learn in-depth how computers works.

Thank you very much for sharing!

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Marcel van Kervinck wrote 05/30/2018 at 21:38 point

Thanks! This project has been a blast, and still is...

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Marcel van Kervinck wrote 05/27/2018 at 23:47 point

It turns out there is a Gigatron Service centre in Belgrade. How cool is that!

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Marcel van Kervinck wrote 05/14/2018 at 11:48 point

We have kicked off a Gigatron user forum:

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hosabike wrote 05/04/2018 at 11:17 point

Hello. I have a small question for creators. This design seems damn effective and useful, but I still have to wonder: why exactly something like this wasn't built in late 60/early 70 despite TTL logic was avaiable since 1966?

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Marcel van Kervinck wrote 05/08/2018 at 23:12 point

Two reasons. First but not foremost is that the RISC architecture was not recognised as commercially viable until much later, like 1985 or so. Doing RISC drops your component count by an order of magnitude. Second is that the real hero in this design is the RAM chip. That chip allows for software to do a lot of stuff you would normally do with circuitry. Dating it: if the design were to be retrofitted for slower TV signals of the day, something like this might have existed around 1985 considering part availability. (Mind: slowest VGA speed = 4x TV speed). The CPU-part could still be made from early 1970s logic. The total system would have been expensive because 32KB SRAM (not DRAM) at that time was expensive.

I have scored some amazingly cool milspec SRAM chips from eBay that are from 1988. They *WORK* in the VGA version! In fact they are already 3 times faster than required for that (25ns while 70ns needed). They must have cost a fortune back then.  I did go through a lot of old BYTE magazine's component ads: you can't find such amazingly fast specs in the commercial offerings at the time... Nothing even close.

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hosabike wrote 05/09/2018 at 07:33 point

Thank you very much for your answer, Marcel. So, it was virtually impossible to build in 70s, wasn't it? May be use magnetic core memory instead?

About TV signal - may be it's possible to DIY assemble a simple display device with Gigatron resolution 160*120 (even monochrome) on the 80's technologies? This would solve a TV problem.

And the second question. How hard is it to code BASIC interpreter on this machine? It does have it's own assembler, AFAIK.

The same question applies to OS.

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Julian wrote 05/24/2018 at 03:15 point

"First but not foremost is that the RISC architecture was not recognised as commercially viable until much later, like 1985 or so."  --- I suspect you're right about this, despite the fact that the clearly *were* people in the industry who knew this was the best approach.  Seymour Cray had been building designs that were effectively RISC systems and which dominated the high performance computing world from the mid 60s right up to the end of the 80s, but nobody else really seemed to understand what lesson to learn from that.

"Second is that the real hero in this design is the RAM chip.  [...] The total system would have been expensive because 32KB SRAM (not DRAM) at that time was expensive."

For reference of how expensive: I found an advert from Dec 1981 (which would probably have been about the last date a machine like this could have launched and been commercially successful -- any later and it'd have to compete with the C64) that priced 70ns SRAM at $30/4kilobits, so you'd be looking at about $2000 worth of RAM to build this machine at the time.  That said, I wonder how well it would work with, say, 8KB of fast SRAM for critical parts of the system and 16-64KB of slow DRAM for bulk storage, which would put the build cost at approximately the same price as the retail cost of a C64 at launch.

Updated: I found another advert from 1981 that suggests the first price I found was ridiculously over the top -- although I'm making some assumptions in interpreting it -- Byte vol 6 issue 11 has an advertiser on page 546 selling "2147" chips for $3.15 each... there are multiple manufacturers who used that number, but of the ones I've looked at (Intel and Mostek), 70ns was the slowest they were still producing in 1981 (Mostek had a 90ns variant in 1979, but seemed to have dropped it by 81), so I'm making an assumption that these were in fact 70ns chips.

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Marcel van Kervinck wrote 05/10/2018 at 00:01 point

With pure 1970s components the CPU section could certainly be built using 74LS parts, but something else has to be done around the RAM. At least make it DRAM, slow down the clock to match (which might be ok for slower TV signals). It is difficult to really go back to that era, because RAM chips of those days are practically unavailable now. So it will look a bit different, but either way still be expensive for the 32KB RAM capacity (even if it were DRAM).

About BASIC: it is just a lot of work. Microsoft could become a company precisely because they had done a BASIC and the microcomputers of the day needed it. This project is a bit in the same state. Unfortunately, Bill Gates is doing different things nowadays! There is a proper assembler already written by user at67 on GitHub. It does both the 8-bit native instruction set as the 16-bit vCPU instruction set.

You want several steps:

- Direct or indirect keyboard hookup. Indirect is easy, but a bit cheating. Direct hookup is a harder nut to crack (at least: if you want to stay with the minimalistic spirit of the rest of the system. If not, just use the Arduino).

- BASIC parser/interpreter. Several weeks of full time effort for an "integer basic".

- Some kind of screen editor

If you go all the way, you need to add:

- Floating point package

- Program save capability. (Load is already there.).

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hosabike wrote 05/10/2018 at 18:05 point

Thanks again. So is it possible to code some network drivers to connect this thing to Internet? At least it seems capable to support some kind of relatively easy protocols like IRC or whatever.

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Marcel van Kervinck wrote 05/24/2018 at 07:07 point

@Julian : I'm interested in that 1981 reference to 70 ns SRAM, because it helps date this project. Do you have a URL or can you scan a copy for me if it is from a magazine?

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Marcel van Kervinck wrote 09/29/2018 at 08:17 point

We did more archeology. Personally I always believed that the SRAM was the anachronism in the design, but it turns out not the case: Julian has been digging into old BYTE magazines for us, and surprisingly, 2147 (4096x1bit) "high speed" or "arcade" SRAM was available for $3.15 in... 1981. Ebay lists such parts with date codes as early as 1978. The slowest grade mentioned in data sheets I can find is 70 ns, and the March 1980 Intel application note AP-74 talks about speeds of 55 ns as if it is old news. I'm completely surprised by all of this. It's part of an interesting quest to date the Gigatron.

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Hacker404 wrote 09/30/2018 at 11:52 point

Some things -

$3 then is about $20 today or more

It's one bit so you need eight of them, that would be $160 or more

They draw 0.8W@70ns so that 6.4W for 8, better go back and redesign the PSU

DRAM was much cheaper and was generally 100ns, 120ns, 150ns or 180ns - either one or four bit

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Bob wrote 04/20/2018 at 15:23 point

Kit worked great, placing the chips in position on the foam like that simplified things hugely and the build manual was very clear - my only soldering error was leaving one pin unsoldered which resulted in a strange offset on the VGA signal, till I spotted it.  I'd be keen to learn more about exactly why it is that for instance this clump of 74xx chips are the ALU and that clump are a register, etc - once that kind of info is made available it could be a great teaching resource along the lines of the excellent Elements of Computer Systems / From NAND to Tetris ( which @monsonite once pointed me towards.

Might I suggest Google Groups as a quick & easy way to get a forum community up?

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Marcel van Kervinck wrote 05/10/2018 at 00:24 point

Hi Bob, sorry I missed your update, but I think I saw it on Twitter :-)

We recognise the usefulness for a forum, but we're super busy so we're really in need of helping hands here, otherwise it isn't going to happen anytime soon. If somebody starts one and I like it, I will join threads I'm interested in. I have to say that I find Google Groups disappointing from user point of view, and for this project there are builders and tweakers/hackers and those threads shouldn't mix. The bbCode type of forums are so much nicer in presentation, and they can support two sections under one roof: Assembly and Hacking (no need to divide it up further, I would be against that).

But then also beggars can't be choosers. Now some programming discussions happen on GitHub for example.

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Bob wrote 05/10/2018 at 00:46 point

Google Goups seems to work fine for other similar kits / kit makers e.g Oscar Vermeulen's awesome PiDP-8/i is here!forum/pidp-8 and soon to be joined by PiDP-11/70 here!forum/pidp-11, Spencer Owen's excellent Z80 kit RC2014 is here!forum/rc2014-z80, Chris Davis' Altair-Duino is here!forum/altair-duino, Julz' Forth-based Fignition is here!forum/fignition, etc - I imagine a number of your customers / readers are, like me, already denizens of these places.

  Are you sure? yes | no

Marcel van Kervinck wrote 05/10/2018 at 01:03 point

I'm aware. Let me say I have just have no real positive experiences with Google Groups. The groups I know and sometimes check out feel disconnected to me and the overview and content presentation is poor, as if it is still running on Usenet. Also no inline images, no markup. I find it frustrating to use for technical content, and therefore groups is not something I would personally frequently checkout and become like a home.

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Marcel van Kervinck wrote 05/10/2018 at 08:21 point

We could be looking into bbPress as forum plugin for on the main site... Any experiences with that? Good or bad?

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Marcel van Kervinck wrote 05/12/2018 at 19:56 point

We're looking at phpBB now... Either self-hosted, or we're going for a rental scheme.

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lion mclionhead wrote 04/14/2018 at 20:41 point

Interesting video from 8bit guy.  It's sort of extraordinary that the gigatron outperforms a VIC 20 using only discrete logic gates for a CPU, but the trick is using modern memory chips & cost.  If it just drove a serial port instead of driving a CRT, it could run much more powerful demos.  8 bit guy was hard on it because he only saw the default firmware spending all its clockcycles driving the CRT.  

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Marcel van Kervinck wrote 04/14/2018 at 21:02 point

We absolutely love his episode! We don't think he is hard on it at all... He presents the project in a superb manner. As he mentions at the end, the programmability is a matter of software, and it is the next phase of the project. The Apple-1 didn't come with a built-in BASIC either, for the same reason: it takes time to build a software environment.

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Ruud van Falier wrote 03/27/2018 at 09:57 point

Such a cool project and also very extensive!
Ordered the kit and built it this week:

Now for diving into the mechanics and figuring out how everything works exactly :-)

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Marcel van Kervinck wrote 03/27/2018 at 10:18 point

So cool to see it work!

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Stuart Longland wrote 02/24/2018 at 21:47 point

I'm guessing the tail end of "On The Turning Away" heard in the bouncing ball video is an artefact of something playing elsewhere in the background and not being played by the computer itself?

Still, damn good effort for purely TTL.

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Marcel van Kervinck wrote 02/24/2018 at 21:52 point

Thanks :-) It can make proper bleeping sounds though. It has 4-bits sound output (16 levels) and the default loop squeezes 4 software channels through that. They can synthesise pulse, triangle, sawtooth, etc. It sounds crappy but charming, just right!

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Stuart Longland wrote 02/24/2018 at 21:56 point

Given a lot of music was constructed with those four primitives… that's probably just fine.  The SID chip does similar with 3 voices.

My only concern here is look out for the DMCA trolls, while it's clear to us (and anyone with intelligence) that the music is just co-incidentally playing in the background … some lawyer might have a momentary lapse of reason and declare the entire video a derivative work. :-)

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Marcel van Kervinck wrote 12/26/2017 at 07:12 point

Anyone attending 34C3 in Leipzig this week: we will be strolling around, and of course we'll bring Gigatron prototypes!

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monsonite wrote 11/08/2017 at 18:28 point

Hi Marcel,

Great work!  Faster, simpler and cheaper than the original IBM PC - love it!

Is there a schematic available for your design?  I'm interested in the final approach you took for your ALU.

Interested to hear some more about the virtual machine you hinted upon.

I have shared your work with

Well Done


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Marcel van Kervinck wrote 11/08/2017 at 19:10 point

The full schematic might appear in some later stage as it is quite a mess in need of serious cleanup and I'm working on software the upcoming weeks. But the ALU is described adequately elsewhere: the "Logic" stage comes from here  (bottom of the page) and the ALU uses two of those with two 4-bit adders, as described here:  except that my design does without the 3rd stage that only provides right-shifting. So in total it is 8x'153 and 2x'283 with 5 control signals going in. Dieter's pages suggest that you need 8 signals, but most of them have the same value for the common operations. The carry-out goes back into the condition decoder where it acts as an allzero-indicator during jumps. There is no flags register as it costs too many chips for too little added value. I do right-shifting in software using the "single-instruction subroutine" technique described in the log on pipelining. This computer doesn't need shifting that much because the graphics layout is 1 byte = 1 pixel.

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monsonite wrote 11/11/2017 at 18:33 point

Hi Marcel,

I'm suitably impressed with the elegance of your design that I have taken time to transcribe it to EagleCAD, so that I can get a better understanding of the control and data paths.

After pondering your Control Unit schematic for an hour yesterday lunchtime, and how it decodes the ALU instructions and generates the various addressing modes and jumps, I was happy that I could figure from the bus and dataflow diagram how most of the rest of it worked. 

Now that the bulk of the design is captured, I'm figuring out a way of using an ATmega1284 as an easy to update ROMulator device, running code from faster RAM and a way of extending by adding more VRAM.

When you consider that the first Sinclair ZX80 machine took 18 TTL chips, plus Z80, ROM and RAM to create a monochrome TV picture of 32 x 24 8x8 characters, for just another 18 chips they could have replaced the Z80 and had something that produced colour graphics and ran at 4 or 5 times the speed.



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Justin Davis wrote 01/02/2018 at 16:51 point

I don't think schematics are ever really "finished", but the schematic that the layout was made from would be most helpful even if it is a mess.  I would like to see them because I would like to try to recreate it in an FPGA.  You could post them now, and then replacement them with a cleaned up version once you have it finished.

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Yann Guidon / YGDES wrote 10/28/2017 at 12:41 point

Amazinger :-D

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f4hdk wrote 05/26/2017 at 11:34 point

I like it! 

Every homebrew computer should have video output, even made with TTL!

Have you seen my project? It is quite similar (custom CPU architecture, video output) even if I used an FPGA  instead of TTL components.

It's fully documented and open source. 

And welcome on the "homebrew CPU Webring" !

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Marcel van Kervinck wrote 05/26/2017 at 13:52 point

Nice! FPGA's are a step up for me. Clearly the TTL and the RAM size are limiting my video resolution, but it is also cute in its own way.

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