75x40 mm, 6 layer PCB, Xilinx XC7Z7010 FPGA, dual core ARM Cortex-A9, 32Mbyte Flash, SD, microSD, Bluetooth, 100 mil headers, single 3.3V
Revision 2 board is still being revised and some work is done to investigate different form factors and feature list that will on board.
First time we have zynq loading the bitstream directly from SD card. Xilinx own solutions do not support this!
Revision 1 schematic released, uploaded to opencores. This is our "ups" version we never intended to produce it, but it happened. R1 is fully working, but we one production run was manufactured for early adopters.
And here we go:
iSDIO or SDIO or SD ? That may be the question, but no longer! iSDIO it is!
The SD Card slot (bottom side, not visible) is designed to support iSDIO. Unfortunately FlashAir version 1 does not support much of the iSDIO at all. So I am waiting for some Amazon orders to arrive, FlashAir rev 2 and PQI WiFi.
What I did not know til yesterday: FlashAir R2 can use be used as 5 bit GPIO Output, this feature is also supported on OZOM, as the SD Card pins can be redefined to be GPIO pins. In that case the top mounted microSD is still available for mass storage, or logging applications. Of course the "shared memory" access to comman RAM area on FlashAir from the WiFi network AND from the ARM Cores. Cant wait the R2 card to arrive!
Electric Imp is also supported, I happened to buy 10 some while ago, never used much. But their online tool was pretty cool. The SHA chip that is requried for Electric Imp to work is added on the board.
And for those who really need to hack with linux, there is an option to plug in some AK2000 based WiFi card. I have the AK2000 SDK laying around waiting to be hacked. AK2000 can also do iSDIO over commands 48/49.
Here is the answer to the Quiz: 90!
On the very first panel, LS Research BT Module was soldered down 90 degrees wrong. It is easy to see that the antenna matching ceramics is not aligned with the RF output!
The open source bluetooth stack BTstack (dual GPL + commercial license) has been compiled for Zynq the code does even fit into OCM, well we do not need it as we have plenty of flash space for code, but for development purposes its easier to load the code into RAM for fast debugging.
This just the first successful compilation of BTstack in Xilinx SDK 2014.4, the HAL layer is not implemented, BLE support is excluded.
Board testing is often overlooked at the design stage, so was it with the first version of the PCB's..
Ingun visiting us, OzOM-A PCB rev 1 on the demo fixture.
This how the fixture looks like, really smooth movement and really easy to change the top and bottom parts of the replaceable fixtures.
And important to know: minimal recommended test-point is 0.8mm! So rev 2 gets 0.8 mm TP's one the bottom side, test points on both sides are possible too, but better not!
The boards got manufactured somewhat in a rush so one 301k resistor was missing, had to be hand-soldered. Luckily it was 0402 sized and not 0201, so I did not need to use microscope to replace it. After that heart pumping, pushing in cables from lab supply to power up the board... as I precaution I am used to turn my face away from the victim that is connected to power first time. This time it was boring, power consumption looked good and the inverse LED on the FPGA Done pin did lit as expected.
JTAG or not JTAG that is the question. Pushing in usb-jtag adapter into the 6 zikzak holes next to FPGA. Vivado hardware manager, auto.. JTAG scan success. We are ready...
PCBs that arrived yesterday
did manage into the oven and out today!
Does not look that bad, but the next batch we use standard green mask. No more experiments with blue.
Quiz: there is big problem visible on the photos, can you tell it as single number? Two digits please..