Soft Propeller

DIPFORTy1 "Soft-Propeller" Zynq-7, Dual CortexA9+ FPGA
DIP40 Parallax Propeller I compatibles footprint

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I have used Basic Stamp I, Scenix SX, all done by CHIP Gracey. I have never used Parallax Propeller, but now I will, implemented in FPGA logic, as Soft Proppeller.
Thank you Chip for releasing Propeller 1 verilog source code.
Of course this DIP can be used small FPGA board or Microcontrolller with custom periperals thanks to the ZYNQ on board.

System Design

Main Components/Features

  • Xilinx ZYNQ-7000
    • Dual ARM Cortex A9
    • 256K OCM RAM
  • 16MByte Flash, also useable as linear ROM
  • MicroSD Socket
  • Sil1143 Proximity and Ambient light sensor
  • DIP40 (Reversible pinout, not burning is inserted wrong!)
  • 3 times 5x2 pin-headers
    • JTAG + 2 I/O
    • 6 I/O
    • 4 I/O
  • Open Source Hardware


    • Hardware design
  • GPL
    • Propeller 1 Verilog

Note: propeller verilog was released under GPL, later there was offical statement on Parallax forums that commercial use is also acceptable without need to stick to GPL. This should be verified however. It seems some old forum threads have vanished. In any case once release under GPL can be used under GPL as this can not be revoked. And the use of Propeller code is not all required, it is just on possible use case.

  • 1 × XC7Z010 Logic ICs / Programmable Logic: FPGAs
  • 2 × EN5311 Power Management ICs / Switching Regulators and Controllers
  • 1 × RGB LED
  • 1 × si1143 Sensors / Proximity
  • 1 × S25FL127SABMFV10 Memory ICs / FLASH Memory

View all 7 components

  • Baseboard is being designed too

    Antti Lukats09/29/2015 at 19:38 0 comments

    While Soft-Propeller can be used on solderless breadboard, it is still good to have some base where it can be used and tested so that is now launched as separate project #HackBerry Pi

    It converts the Soft-Propeller into RPi form-factor and allows to use RPi hats

  • IT runs propeller code too :)

    Antti Lukats09/14/2015 at 14:02 0 comments

    While it was advertised as SOFT-PROPELLER, it was not until today it actually works as a Propeller.

    Testing on Parallax Development Board, flashed the SPIN code into EEPROM on Parallax board, and well Soft-Propeller configures itself from SPI flash as propeller and then loads prop code from EEPROM.

    Soft-Propeller has no on-board EEPROM, but this can be emulated in FPGA there are enough block rams free.


    FF: 15%

    LUT: 50%

    BRAM; 33%

  • MULTIBOOT Flash Image ready

    Antti Lukats09/13/2015 at 19:37 1 comment

    This may sound like small thing, but we have ready to ship Flash image that can either boot ARM Code from SD Card, or then execute multiboot process and configure every thing from second (application) Image in Flash.

    The second image could be Soft-Propeller or any thing else.

    Of course the code that would be loaded from SD Card can also configure the FPGA and load more software code from the SD card or the Code loaded from SD Card can update the Application image in Flash, so with next reset without the SD Card the new application would be loaded from SPI Flash.

  • Prop gets more memory

    Antti Lukats09/11/2015 at 09:51 1 comment

    DIPFORTy2 - a version with external memory and usb and hdmi seems to possible also.

    After doing 90 degrees turn the RAM routing looks doable, this is the most dense ZYNQ+DDR routing I have done so far:

    This may not be so impressive, but LPDDR2 with 0.65 mm pitch is directly under Zynq BGA with 0.8 mm pitch, and HDMI signals have be routed through the memory routing area, all this on PCB with no HDI technology, no buried no blind vias.

    It so often looks impossible until you just do it. LPDDR2 is directly below ZYNQ BGA, all signals routed in top bottom only, not internal signal layers used.

  • Propellers to Finland

    Antti Lukats09/10/2015 at 14:12 0 comments

    First Soft-Propellers left base, heading to Finland. Shipments to the rest of the world will go out next week.

    And we work on the documentation too, we do!

  • SD Card Bootloader working

    Antti Lukats09/09/2015 at 14:58 0 comments

    This may sound like a minor thing, but loading from SD card in the system with no external RAM and no bootrom bootable SD card is really tricky. Well its working now. Later the bootloader will possible use XiP, right it is like this:

    FSBL is loaded from Flash

    FSBL loads FPGA BITSTREAM from SPI Flash

    FPGA "adds" 128K RAM accessible to the CPU0

    FSBL loads SSBL from SPI Flash into RAM in FPGA

    SSBL Loads S-Records from file on the SD card into OCM RAM

    Your code from SD Card is running.

    At this point the RAM in FPGA is no longer used and we can re-program the FPGA from file on SD card, or update the SPI flash from SD card..

  • WS2812 IP Core Testing

    Antti Lukats09/07/2015 at 21:29 0 comments

    Vivado IP Catalog, click click.

    Vivado IP Integrator, click click.

    Xilinx SDK (Eclipse):

    void SetWS28xx(u8 RED, u8 GREEN, u8 BLUE) { putfsl(RED << 16 | GREEN << 8 | BLUE, 1); }
        while (1) {
        	SetWS28xx(r, g, b); //
        	r++;  	g++;  b++;
    Solder iron, first convert WS2812 to SIPSIK(tm) compliant device, that easy just solder some header!

    Get 3 wires

    Connect the wires


    Get Oscilloscope, power it on

    Can not wait? Look at the wires again, SWAP ground and signal and

    you will see

    That WS2812 does work, and is controlled by software.

    This is first time I ever used WS2812.

    As soon as fixed the problem with the wiring, it just worked, namely:

    1. CPU0 Bootrom did load FSBL into OCM ram
    2. FSBL did load FPGA code that is the "HARDWARE" from an partition in the SPI Flash
    3. This BITSTREAM was DMA'd into ZYNQ PL - Programmable logic
    4. PLL in Processor part of ZYNQ was set to deliver clock to fabric side
    5. In the Programmable Fabric an 32 Bit Soft core MicroBlaze is booting from Block RAM that was loaded together with the bitstream during the FSBL boot proccesses
    6. Microblaze exectutes the main.c - code above
    7. The c code uses special processor instruction that directly writes the data to streaming hardware port
    8. This data is latched in WS2812 IP core
    9. The IP core generates the timing
    10. WS2812 is controlled by the software :)

    You think this can not be true?

    That this all just works first time tested?

    Well then you would not believe I can do #HAD-9000 in 2016 either?

    Without your help, I can not. With your help WE can.

    Would you like to work on HAD-9000 ? You can.

    You can start now with Soft-Propeller, its gives the boost you need to be ready for HAD-9000 in 2016.

  • SDSoC first tests

    Antti Lukats09/07/2015 at 20:20 0 comments

    This is exciting, I think in the next year it will mature, Xilinx SDSoC

    To cut the bla, its really simple: You select platform, say Soft-Propeller, in Eclipse, write some C code, and you get ready to run image that works on the ARM Cores and is partially compiled directly into FPGA hardware.

    This works now. It does! SDSoC 2015.2 is first public release so expect some issues, but the basic flow really works.

  • 59 EUR - Lowest cost ZYNQ mod ever!

    Antti Lukats09/07/2015 at 09:57 0 comments

    DIPFORTy1 "Soft-Propeller" is

    1. Lowest Cost ZYNQ based Module ever made
    2. First ZYNQ module that can use existing bases and project boards (Parallax Propeller chip compatibility)
    3. First ZYNQ based product ever in Hackaday Prize semifinals
    4. First Xilinx 7 Series based product ever in Hackaday Prize semifinals


    Order link

    Note: TE0722 - warehouse software assigned number :)

    Note 2: the Hardware Design files are on github...

  • Prelimary pricing, docu-wiki!

    Antti Lukats09/03/2015 at 10:50 3 comments

    Price: 69 EUR

    This makes it lowest cost Module with Xilinx ZYNQ technology avaiilable.

    Order now


    new name, DIP40 = DIPFORTy

    Number 1 is sub-product type: DIPFORTy1 is first one in the family with code name "Soft-Propeller"

View all 22 project logs

Enjoy this project?



toshas wrote 10/20/2016 at 07:06 point

Now I can see both revisions in stock on Trenz website.
Could you explain what is the difference between REV1 and REV2. I mean what kind of SCH/PCB bugs you solved in REV2.
Will REV2 sources (AD project) be uploaded on github ?
Thanks a lot! It's amazing project!

  Are you sure? yes | no

David Betz wrote 03/11/2016 at 03:57 point

Any update on the availablity of this product? I still haven't received the one I ordered.

  Are you sure? yes | no

David Betz wrote 12/11/2015 at 03:57 point

Has anyone ever received one of these modules? I ordered ages ago and have heard nothing.

  Are you sure? yes | no

Antti Lukats wrote 12/11/2015 at 09:28 point

we just have REV 2 PCB manufactured, they are on hold until i release the factory image for flashing..

  Are you sure? yes | no

Jac Goudsmit wrote 10/09/2015 at 22:51 point

Hey Antti, what source code are you using to program the FPGA? I don't see it in the repo. If you have it elsewhere in Github (or on another public Github server of course) I would like to branch/merge/integrate your Verilog code into my P1V repo at Thanks!

  Are you sure? yes | no

Leon Heller wrote 09/30/2015 at 10:29 point

I've just ordered one from Trenz.

Antti assembles them to order (2-3 days). Cost was 70.21 Euros:

Email them first, and don't take any notice of the zero stock.

  Are you sure? yes | no

Antti Lukats wrote 09/30/2015 at 10:31 point

well we have small stock, but the TESTING is currently on my desk still, yes..

  Are you sure? yes | no

Djs wrote 08/21/2015 at 09:14 point

how can we buy one board?

  Are you sure? yes | no

Antti Lukats wrote 08/21/2015 at 09:23 point

just send email, they are not in online shop, but we have them ready to ship :) !

  Are you sure? yes | no

Glenn wrote 08/23/2015 at 18:06 point

HI Antti, what will be the cost in USD?

  Are you sure? yes | no

hatakilkn wrote 07/27/2015 at 06:48 point

Hello, Actually i am working on a project using Zynq7000 Socs, but i need more IOs in my design. How many IOs is it possible to add to your project?


  Are you sure? yes | no

Antti Lukats wrote 07/27/2015 at 07:24 point

in dip socket are 34 io, if you count all connectors then 42 io + 3 more input only pins are available

  Are you sure? yes | no

hatakilkn wrote 07/27/2015 at 07:36 point

Excuse me, you mean that I can use 45 more IOS and this board countains already 34 IO ?


  Are you sure? yes | no

Antti Lukats wrote 07/27/2015 at 10:02 point

no, sorry: in the DIP40 header: 34, in the other headers: 4 + 6 + 2 + 3 input only, so abs total max use: 42 + 3

  Are you sure? yes | no

hatakilkn wrote 07/27/2015 at 10:54 point

In my project i will be using about 80 IOS, is it possible to redesign the PCB and extract more IOS for example or what do you advice me to do.


  Are you sure? yes | no

hatakilkn wrote 07/27/2015 at 10:59 point

and excuse me for this question what is the designation of the NAND Flash, because the documentation doesn't indicate.


  Are you sure? yes | no

Antti Lukats wrote 07/27/2015 at 11:01 point

16mmyte quad spi serial nor flash, can be accesses as XiP linear memory also, no nand

  Are you sure? yes | no

hatakilkn wrote 07/27/2015 at 11:17 point

Thnks for the informations, but what is its reference in the Design that you putt in GitHub ?


  Are you sure? yes | no

Antti Lukats wrote 07/27/2015 at 12:05 point

Nothing yet, but for sure there would be propeller demo, and some logic analyzer, and maybe something else to get started.

I am on vacation actually, so my time is clustered and limited atm.. hence the random replies

  Are you sure? yes | no

Antti Lukats wrote 07/27/2015 at 14:15 point

Clg225 has total 54 fpga io and some on the processing system so with package 80 io is not directly possible. But if your system includes slow and fast peripherals you may add io by using say simple serial registers fpga can scan them very fast

  Are you sure? yes | no

Jorge Lacoste wrote 07/22/2015 at 16:06 point

Are you going to be posting the design files? I would be curious to see the schematic and layout documents. Which tool did you use to do the board layout?


  Are you sure? yes | no

Antti Lukats wrote 07/22/2015 at 18:53 point

Altium, and yes will get published the CAD source files.

  Are you sure? yes | no

CarlosL wrote 07/23/2015 at 13:59 point

Oh so great.

By the way, if you release the CAD for OZoM before this you round my day.

  Are you sure? yes | no

Antti Lukats wrote 07/23/2015 at 20:21 point

ozom-a CAD files are actually released, they are on public access SVN server, with not so widely known url.. i try to change this, probably by duplicating the sources to github or somewhere else

  Are you sure? yes | no

CarlosL wrote 07/25/2015 at 11:14 point

Oh! so far so good :D

Can you post the URL on indegogo page? We're waiting like KIDs on christmas.

Thanks for your job,

  Are you sure? yes | no

Antti Lukats wrote 07/25/2015 at 11:58 point

uups, the SVN path was not visible, I was mistaken, so:

this are the original sources for the first batch manufactured, I push the info to other places too

  Are you sure? yes | no

Antti Lukats wrote 07/23/2015 at 20:21 point

ozom-a CAD files are actually released, they are on public access SVN server, with not so widely known url.. i try to change this, probably by duplicating the sources to github or somewhere else

  Are you sure? yes | no

Victor Suarez Rovere wrote 07/19/2015 at 00:01 point

can you run more than 8 cogs? How many LE are available now?

  Are you sure? yes | no

Antti Lukats wrote 07/19/2015 at 11:51 point

see project log, I compiled prop v1 code for 7010 its about 50% of LUTs. Xilinx does not count LE as Altera. Bit more than 50% of LUTs are used from other resources less than half.

  Are you sure? yes | no

Antti Lukats wrote 07/17/2015 at 18:33 point

BGA is simple both for manual as for automatic assembly. As long as you do not go below 0.8mm pitch, you can use pretty much any PCB fab. The fab we use for small batches does have production panel size of 360x460mm, and no discount on repeated order, and prices go up if you order more boards. You pretty much pay for the full 360x460mm always, or it does never make sense to order less than 1 full panel (this could be your multiproject pcb with 50 projects..). The price of one panel is from 300 to 1000 eur. I do not recall what the DIP40 boards did cost, it is OK for first runs, for larger volume we need to use other fab. For small runs:

you can check out their capabilities :)

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TommiRouvali wrote 07/17/2015 at 18:19 point

Hi, cool project! Can you comment on what PCB factory you used and how much that one panel cost? I have done some Spartan 3 and Spartan 6 projects with TQFP-package and 2 layer PCB. But all good stuff seems to be packed on BGA:s now days, so I am very curious how to get there.

  Are you sure? yes | no

Antti Lukats wrote 07/16/2015 at 10:53 point

We produced 1 pane = 4 PCBs, we had 5 pieces of ZYNQ for $$$ money, we have ordered from "quote pricing" - but this takes some time to arrive. But we do our best not to delay. We have some PCBs from first batch, stencil is there. So we do more testing, and then its up to Avnet when they deliver the Zynq.

  Are you sure? yes | no

DaveG wrote 07/16/2015 at 09:36 point

This is awesome! Now shut up and take my money!

  Are you sure? yes | no

Antti Lukats wrote 07/16/2015 at 07:03 point

it is 6 Layer PCB, yes I will post more pics, the board just was produced yesterday so I had no time to make real photos, just with my handy some quick shots..

  Are you sure? yes | no

Djs wrote 07/16/2015 at 03:53 point

This is a great product that I wish to have couple of them, can you please post the back side pictures?

  Are you sure? yes | no

S J wrote 07/15/2015 at 20:58 point

This is amazing. I'm so excited to see a ZYNQ board :)

Just out of curiosity how many layers does the PCB have? 

  Are you sure? yes | no

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