I loved electronics as a kid before other priorities took over. Then one day on a training ride my GPS battery died and I credit that moment with getting me back into electronics. That was some years ago and looking back the design is primitive and probably shows where I left off as a kid.

Nonetheless I use it to this day and it has never let me down. It's performed in all kinds of climates from freezing to 100+F with sustained speeds in the mountains of 40+mph. So I figure it's worth sharing.

The TRIPLE5dps is a SMPS designed for bicycle hub dynamos such as the Schmidt SON or Shimano Alfine.  It was my first serious work in many years and is a discrete component design using three (yes 3) 555 timers.


Note:  the zip file in the files section contains the Eagle schematic, board, and parts library along with the parts list in Excel.


The TRIPLE5dps gets its name from the use of three 555 timers to perform the PWM, duty cycle control, and limit  functions.  It is truly amazing that in our culture of disposable technology the 555 timer is still in mass production forty plus years after its debut.

The TRIPLE5dps is a fixed frequency PWM running at 100KHz, utilizes a buck topology, and delivers 5VDC within -3%, +0% with less than 50mV ripple up to 1A.  Included features are input over-current protection, output over-volt protection, and output current limiting.


The dynohub’s AC input is connected to the rectifier section through two fuses.  F1 is a slow blow 1A fuse and protects against an internal failure and is used to allow for in-rush current to charge C1 that will occur when connecting to a DC power source such as an automotive power outlet.  Do not connect to utility AC!  F2 is a thermal fuse bonded to the heat sink tab of Q1 and disconnects the AC input via heating from Q1 when an over-volt condition develops on the output.  Diodes D1-4 form a full wave bridge rectifier with filtering capacitor C1 to provide the working DC buss voltage used by the power supply.

Transistors Q5, 6, and 8, along with R4, R6, R7, C3 & C4, and D6 form a simple linear regulator that is used to power the control circuits.  It provides a regulated 12VDC and 10mA of current.  Because the control circuitry only requires a working average of 7mA, pass transistor Q8 can tolerate the voltage stress without excessive dissipation.  This design keeps allows the use of a cheap off-the-shelf choke by eliminating the need for a secondary winding & associated circuitry.

The PWM core is comprised of three 555 timers.  Two are housed in the 556 package (timer #s 1 & 2), and the third (#3) is a stand-alone 555.  All three are the TLC CMOS variant to reduce power consumption and improve switching performance.  The PWM is divided into three operating sections:  ramp generator, duty cycle control, and PWM.

Timer #1, Q9, Q10, R9, and C6 generate a linear ramp timing signal used by other sections of the PWM.  Q9, Q10, and R9 form a constant current source and together with C6 set the ramp frequency.  The ramp signal is used by timer #2 along with R21 to establish duty cycle limit timing (~50%).  The square wave output of timer #2 drives the reset pin of the PWM (timer #3) low when the duty cycle limit is reached which turns the PWM output off.  The duty cycle value is set based on the maximum output load of 1A at the minimum DC buss input voltage of 12V.  Timer #3 serves the PWM function and sets the output duty cycle based on the control voltage from error amp U2B.

U2 is a TLC272 CMOS dual precision op amp.  Voltage mode control is employed by U2B to maintain regulated output.  U4 & R19 provide a precision voltage reference, and the output voltage is sensed by R16 & R18.  R15, R17, C8, and C9 set the gain curve for the error amp.  U2A performs output current limiting.  The voltage differential across current sense resistor R13 is monitored and as the inverting input voltage approaches the non-inverting value, U2A’s output voltage will rise.  R10 & R11 set the voltage differential at 100mV which represents 1A.  R12, R14, and C7 set the gain curve for U2A.  At the set current limit U2A’s output voltage will be sufficient to turn on the gate of Q11 which will reduce the control voltage of timer #2, thereby reducing the duty cycle limit.  This design has a foldback characteristic, and with a short circuit both output voltage & current will be near zero.

Q2, Q3, Q4, and C2 form a level shifting totem pole driver for switch Q7.  R5 charges C2, and D5 ensures that Q7’s gate-source voltage limit isn’t exceeded.  L1’s value is set to keep the inductor in continuous mode down to about a 10% load.  Blocking diode D8 ensures that user equipment containing batteries won’t be discharged when the regulator isn’t operating.  Resistor R22 and LED1 provide a visual indication that the regulator is operating.

Q1, D9, and R20 form a power zener shunt to protect user equipment from an over-volt condition.  Thermal fuse F2 is bonded to Q1’s case and will permanently disconnect the AC line in approximately two minutes when a sustained over-volt condition occurs.


TRIPLE5dps’ net efficiency ranges from a low of 61% to a high of 76% depending on load & input voltage.  At typical bike speeds of 14 - 18 MPH the supply will obtain average efficiencies in the low 70s.  Removing overhead (rectifier, current sense, linear regulator, output blocking diode), the power train runs at about 85% efficiency.  This could be further improved by replacing Q7 with one of lower Rds on & switching latency.

Expect to see a 50C temperature rise in Q7 under typical steady state operating conditions with a load of 1A (input ~ 15V).  At inputs below 30V conduction losses dominate; above that switching losses.  Q8’s dissipation will be highest with high input voltages, which are associated with light loads.  Expect a 50C rise with an input of 100VAC.