The code that calculates the Sigma-Delta "synthetic division" is made of just these 5 lines:
// Sigma delta modulation algorithm using "synthetic division" sum[n] += req[n]; // Update integrator value if (sum[n] < max[n]) outBits++; // LSB = 1 else sum[n] -= max[n]; // LSB = 0 (untached) and adjust integrator
The complete code can be found in the GitHub repository. The rest of the lines from file https://github.com/RoGeorge/Delta-Sigma_versus_PWM/blob/master/main.c is just waving the colors.
- sum[n] is an accumulator, similar with the PWM counter
- req[n] is the duty cycle, equivalent of the PWM compare register
- max[n] is the overflow value for the accumulator
- n is the channel number, in this demo there are 10 independent "PWM like" channels
Apart from the intimidating name, "synthetic division", the implementation is pretty simple:
At each step, add the requested duty cycle to an accumulator. When the accumulator overflows, you set the output to high. If it doesn't overflow, you reset the output to low. Then, in the next step, continue adding from where you were left.
The maximum advantage regarding the refresh rate is at 50% duty cycle, where Delta-Sigma becomes 'max/2' times higher then PWM, where 'max' is the overflow value.
As an example, for an 8 bits PWM at 50% duty cycle, Delta-Sigma has a refresh rate 128 times higher then a PWM. For a 16 bits PWM, the Delta-Sigma would be 32768 times better at refresh rate.
One more advantage is that Delta-Sigma is more responsive. You can modify the duty factor on the fly, without waiting for the whole cycle to end. Of course, you can also choose a different resolution for each channel by modifying max[n].
3D Printing AVR Arduino Art Audio Automation BeagleBone Bluetooth Cameras Clock Drones Environment Hardware IoT LED Medical Music Radio Raspberry Pi Remote Control Robotics Rockets Satellites Science Security Software Virtual Reality Wearables