FPGA: What they are when to use and when not and if then how?
Xilinx is de-facto the FPGA company. The biggest and...
For me Peter Alfke was Xilinx, the one who made Xilinx.
He is no longer able to influence the development of Xilinx.
I do not know if there would have been a difference, maybe.
As of today Xilinx message is clear, this can be read from their website
The smalest FPGA Xilinx has today, is Artix A15T.
You can fit an 32 bit SoftProcessor + MMU + DDR Controller IP Core + all peripherals that are needed to boot standard Linux into A15T.
When I started with Xilinx FPGA's their FPGA had 64 Flip Flops. It was fascinating back then.
It is REALLY fascinating now.
Go take the path, go for 7.
As FPGAs can have many things working in parallel and may not contain an embedded processor at all then special tools are used for debugging. Most FPGA vendors have "embedded instruments" that can be added to your design and that provide visibility into the hardware.
Xilinx - Chipscope, now Vivado Labtools (requires paid license)
Altera - SignalTap (free)
Lattice - Reveal (free)
Microsemi - need to figure out
There are some attempts for platform neutral or cross platform embeded instruments, Altium is/has tried this and opencores OpenRisc seems to have something too.
Sump LA can of course also be used for internal debug..
There is no one winner.
We can not always avoid the use of "glue logic" - this is fine, as long it is limited to few tiny logic gates or so.
If we need more, then it would maybe already make sense to implement this "glue logic" in CPLD.
Wait CPLD's do not exist any more. They have been replaced with small FPGA's now!
Example, if we need:
We can of course use still glue logic and level shifters, but we may already consider using Lattice machXO2-256 in QFN32 package.
So simple replacement of some small glue logic may get an FPGA into the game.
The benefit? We do not need to source the different components (the logic ic, the level shifter IC), we just take the one part we have in stock, the FPGA and implement that logic.
This is real world example of real product.
This could be done as: small CPLD as glue that helps with the "custom protocol" + some MCU - the classical solution.
If we add the prices of CPLD + Flash MCU, we end up at say 3 USD at least.
Small FPGA's are also in that price range - so in this example a small soft-core processor was fit into the FPGA along with the custom logic. The soft-core was very simple and had very small code memory, so it required a lot of optimization on the software side. But as it was targeting volume production this optimization did make sense.
This was many years ago, there are new FPGA's families out now, and you can get more for the same price now.
This is one example where "MCU was eliminated" and where it also made sense - the price, that FPGA did also cost about 3 USD and it replaced BOTH the CPLD and MCU together.
Simple replacement of MCU in project where MCU can handle it all usually does not make sense.
The definition has changed and is changed, the best description would be that they are "programmable hardware" based on architecture that is "scale-able" like an array. This scaling in 2 directions makes FPGA's different from classic CPLD's where prices of the silicon go up very quickly when the CPLD goes larger. This is the reason why classic CPLD's are vanishing - they are being replaced with small FPGA's that fill the gap. Altera MAX 2, V, 10, Lattice XO2, XO3 can be considered as CPLD, and they target some CPLD markets, but they are actually small FPGA's as of the architecture.
Simple logic circuits are arranged in 2 dimensional array, with programmable interconnect. Very large FPGA's are 3D in that sense that those 2D arrays are layered with additional "vertical" interconnections.