TEENY : Open Network Analyzer

Pocket Sized Network Analyzer that can be used to measures the network parameters of electrical networks.

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A network analyzer is a very expensive piece of test equipment that is locked down in a college or research laboratories and usually out of reach from Engineers, RF enthusiasts, and makers. This project aims to bridge the gap enabling Makers, RF enthusiasts design, build and test their
RF design which was not possible before
The main objectives of the design
- Low Cost
- Scalable design
- Pocket Sized
- Open and hackable
This project is under prototype stage we designed revision one of TEENY, Which use STM32F103 as the main microcontroller and AD9851 which is a DDS signal generator for generating the test signals. After signals passing through Filter, Amplifier and DUT(Device under test) output are measured using a power detector. In the next stage, we wish to replace DDS with a PLL which will be a Vector network analyzer and goes from 0 to 1.5GHz. We are hard at work designing the second revision.

RF seems to be a lot like black magic there are multitude of things that are taken in consideration while working with RF design especially above few hundred Megahertz . As a electronics engineer i love to tackle problems like this .This project came to me when i designed passive filter for a project i had no equipment to test the real world performance of the filter after searching few hours in internet i stumbled upon an arduino shield  to measure network parameters  and few other projects, Keeping all this in mind we started designing the first revision of network analyzer . 

    We choose STM32F103 mainly because it support full speed USB communication and its in-build ADC is better compared to ADC found in microcontrollers like avr and pic series another fact that narrowed down to STM32F103 is because popular ARM development board "BluePill" use this same microcontroller which is easily available in most electronics stores. When we talk about DDS Analog device is first manufacture that came to my mind they have a extensive line up of DDS, Searching through their website there was not  much difficulty in choosing AD9851  it goes from 0 to 180MHz but presence of harmonics limit usable range is between 0 to 70 MHz . We had to design a filter in order to knockoff higher harmonics . AD provide an online simulator to simulate their DDS this came handy in designing DDS part of the circuit ! Many simulations are done using LT spice especially designing the 7 th order butterworth filter  and amplifier. The signal from DUT is connected to power detector and output from detector connected to ADC . A custom software interface  for TEENY is written in python. 

In second revision of TEENY can measure both amplitude as well as phase making it a fully functional Vector Network Analyzer (VNA) .There are still some more testing that needed to done for our first revision .

GitHub Click Here

Teeny v2 Design Thought Process

Teeny revision one was a scalar network analyzer teeny v2 will be a vector network analyzer this will be huge leap in engineering perspective. We are final year Engineering student from India, sourcing components is very difficult in India Digkey/Mouser offers services in India but the shipping rate is too steep for students like us this is one of the barriers that we are facing right now.

                                                  Teeny v2 Block Diagram 

Teeny v2 will be entirely different from the first version in which we used DDS but the limitation of DDS is that as you increase frequency the price increase exponentially thus we are moving towards PLL based source they are relatively inexpensive compared to DDS and have good price to frequency ratio. Directional coupler is another key element of vector network analyzer a directional coupler that works from few kHz to 2 GHz is required it must be small and cheap (Mini circuit have selection of directional couplers that satisfy all this criteria)

Receiver section of the VNA consist a port selection switch coupled to IF and ADC this design lowers the cost as dedicated ADC for each port will increase Board space as well as overall cost of VNA. FPGA will be used for further processing (IQ modulation) .Lattice MachXO3  looks promising they are cheap small and development tools are open source.

" If we got the right opportunity in one or two years this project could be a Kickstarter campaign "

Teeny v1-Schematics.pdf

application/pdf - 56.48 kB - 03/19/2018 at 09:16


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graham.gunderson wrote 03/25/2018 at 05:00 point

I work with Lattice MachXO3 all the time, it's a great platform for projects like this. I use the $20 FPGA starter kit ( and Lattice Diamond which is provided by Lattice for free. The $20 dev board has enough IO for about anything, and the Diamond IDE will compile a design in about 30 seconds while Xilinx Vivado takes about 4 minutes to do the same job. 

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glenpyeldho wrote 04/20/2018 at 17:41 point

Thanks Graham for the feedback ,Yes their development board is cheap and it fanout almost all of its IO's ! 

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Duke Circuit Co.,Ltd wrote 03/17/2018 at 03:34 point

it would be service in IoT?

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basilvarghu wrote 03/16/2018 at 13:14 point

Great work

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jesuschinchu wrote 03/15/2018 at 10:40 point

good job..

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im_gmk wrote 03/14/2018 at 18:10 point

cool stuff !👍👍

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anupgodwin wrote 03/14/2018 at 17:52 point

Great work. well done.

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Prasanth KS wrote 03/14/2018 at 17:47 point

Well explained! Good One! 

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