60 Results for "rtl-sdr"

Hack Chat Transcript, Part 1
Log from Cyberdeck Brainstorming Hack Chat
Jame511:51 AMA cyberdeck already exists for the billions it's called a laptop jordanbrandes11:51 AMa laptop lacks expression cyzoonic11:51 AMAll my work is open source. back7.co11:51 AMSome of my work is open source, :D jordanbrandes11:52 AMhaving finally...

BoxLambda Architecture, First Draft.
Log from BoxLambda
In this post, we organize the key components from the previous posts into an architecture diagram. Along the way, we identify a few new components. None of what’s shown here is set in stone. The diagrams below contain some speculative pieces and there...

NAND or NOR ? A taxonomy of topologies
Log from PDP - Processor Design Principles
When you start to design a computer, you usually start with rule 1. Use binary, 2s complement numbers (unless you're @SHAOS or @alice crush) but it's only the beginning. You have to choose a technology, which is a complex entangled web of compromises...

NMOS Logic and Discrete MOSFET Types
Log from Discrete NMOS Logic in 2020
The most basic NMOS gate, an inverter, consists of a load resistor and an N-MOSFET as shown below. NAND and NOR gates can easily be formed by using two N-MOSFETS, more complicated gates are formed by combinations thereof.---------- more ---------- Some...

Building Software and Gateware with CMake and Bender.
Log from BoxLambda
Recap This is a summary of the current state of affairs for BoxLambda. We have: An Ibex RISC-V core, a Wishbone shared bus, a Debug Core, internal memory, a timer, two GPIO ports, and a UART core.A Picolibc-based standard C environment for software...

Open Source Chip Design Hack Chat Transcript
Log from Open Source Chip Design Hack Chat
Jack Kang Sure, hi everybody! My name is Jack and I am VP of Product and Business Development at SiFive. before SiFive, I started my career as a front end chip designer, working on bus controllers, memory controllers, and CPUs. then moved into product...

Modes of operation
Log from VHDL library for gate-level verification
Suppose, for the sake of argument, that you want to create a digital silicon chip, for example. The exciting ASIC world is calling your name so your RTL code is tested, formally verified, simulated, cosimulated, and finally synthesised. At that point,...

Check out
Log from Chameleon
19-Apr-14The Chameleon was initially released after the M65C02 project was ported to the board. Simulation of the modified RTL files had not been performed at that time, but a custom FPGA build that toggled all of the output lines was running. The output...

Some FAQs, and dealing with ISE Project Files
Log from ChipWhisperer®: Security Research
First off - I decided to write some FAQs. I was going to add them to the main project details, but I've hit a maximum character limit in my detail! So for now I've copy/pasted them here, sorry for the big old wall of text! I also wanted to talk about...

HACKLET 51 – CROWDFUNDING PROJECTS
Log from Hackaday.io Project
Ah crowdfunding. You might say we have a love/hate relationship with it here at Hackaday. We’ve seen some great projects funded through sites like Kickstarter, IndieGoGo, and the like. We’ve also seen projects where the creators were promising more than...

SDIO
Log from Nyx: Edison - FPGA Devboard
Reverse EngineeringAs I mentioned in my last post I decided to use SDIO as an interface between the Edison and the FPGA on Nyx. The only problem is that in order get the information to design a proper SD host controller and SDIO device you need to pay...

Synthesis and Technology Mapping
Log from VHDL/Verilog to Discrete Logic Flow
This is where things get a bit more interesting. I was concerned that it was quite difficult to coerce Yosys into using my custom gate libraries, but in fact it was rather easy. The "cmos" example proved to be an excellent blueprint to creating a custom...

Hack Chat Transcript, Part 1
Log from Signal Conditioning Hack Chat
Jon Foote11:57 AMHello, this is Jon, hoping I'm in the right place! Indeed you are, welcome Jon! Jon Foote11:58 AMThanks Dan, and thanks for putting this together. morgan11:59 AMhi Jon! long time, how's things? Jon Foote11:59 AMAnd thanks to @Aleksandar...

A detour to Pano Logic G1 (4) - USB
Log from VerilogBoy - GameBoy on FPGA
I promised that there would be an update about the USB, here it is. This update would only talk about the USB 2.0 Host on the Pano Logic G1 devices with ISP1760 USB host controller, so it is probably not applicable to other platforms. The goal here is...

Back and Forth Project Scope Discussion
Log from Project Boondock Echo
KC and I had several back and forth messages through email to determine the scope of the project. (Lots of detail, but you can see the general thought processes below): KC -- check this out: https://github.com/sharkrf/srf-ip-conn-srv And Openspot...

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