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  • AscetiCore ⋅ Data formats
  • Hacker page     by Jock Tanner
  • Natively, i. e. without external devices or coprocessors, the CPU is able to work with two data formats: 8-bit bytes, 16-bit (or two-byte) words. Data bitness can be extended by using specific arithmetic instructions, that take carry flag into account....

  • AscetiCore ⋅ Registers
  • Hacker page     by Jock Tanner
  • From the unprivileged user’s perspective, the CPU have a register file of 16 16-bit registers (let us denote them as R0 to R15 for brevity) and the 16-bit status register (SR). Registers in the register file, with some minor assumptions, can be called...

  • AscetiCore ⋅ Memory
  • Hacker page     by Jock Tanner
  • Memory is an array of cells, each of which holds an 8-bit byte, so terms “byte” and “cell” can be used interchangeably. Each byte can be accessed by its unique 16-bit index, which is called “memory address”,...

  • AscetiCore ⋅ Virtual memory
  • Hacker page     by Jock Tanner
  • The physical address space of the AscetiCore CPU is divided into 4Kb pages. The lower 12 bits of a virtual address is used to address a byte inside the page, while higher 4 bits selects one of 16 page registers (PR0…15). The page register size is 16...

  • AscetiCore ⋅ Context and modes
  • Hacker page     by Jock Tanner
  • CPU context is such a set of data that fully defines CPU state between any two consequitive operations. AscetiCore CPU state consists of: common purpose registers (R0…15), status register (SR) and other special registers, three sets of page registers...

  • AscetiCore ⋅ About instructions
  • Hacker page     by Jock Tanner
  • All instructions are word-sized, except for those using offset addressing (see “Addressing modes”); offset may be treated as an additional word appended to the instruction. Unlike data, instructions must be aligned on word boundaries, i.e....

  • AscetiCore ⋅ Operands
  • Hacker page     by Jock Tanner
  • Operand is an entity the CPU instruction is working upon. Instructions may take different number of operands. Various computer architectures may implement: niladic instructions, that require no operands, like commonly used NOP or HALT, monadic − one...

  • AscetiCore ⋅ Addressing modes
  • Hacker page     by Jock Tanner
  • Addressing is a way for CPU to locate operands used in instruction. Addressing can be explicit or implicit. If an operand is encoded in instruction as a certain bit fields, then it’s an explicit addressing. The CPU has 5 explicit addressing modes: register...

  • AscetiCore ⋅ Instruction types
  • Hacker page     by Jock Tanner
  • Data transfer This type of instructions are made to move data (words or bytes) from one location to another. “Location” can be a register or a memory cell(s). The CPU supports only memory-register or register-register transfer. It means...

  • AscetiCore ⋅ Instruction fields
  • Hacker page     by Jock Tanner
  • Each instruction consists of one or more bit fields. Most important are opcode and format, which have variable length and identifies the certain instruction and its format, i.e. location of other bit fields in it. Those other fields, in turn, have constant...

  • AscetiCore ⋅ Dyadic indirect
  • Hacker page     by Jock Tanner
  • logical instructions Opcode Mnemonic Description Flags 0b0000 AND(B) reg, mem Logical conjunction P, Z 0b0001 OR(B) reg, mem Logical disjunction P, Z 0b0010 XOR(B) reg, mem Exclusive OR P, Z 0b0011 BRS(B) reg, mem Reset those bits of reg set in mem...

  • AscetiCore ⋅ Dyadic direct
  • Hacker page     by Jock Tanner
  • This format mirrors DI, only difference is both operands are register. Opcode Mnemonic Description Flags 0b0000 AND(B) reg1, reg2 Logical conjunction P, Z 0b0001 OR(B) reg1, reg2 Logical disjunction P, Z 0b0010 XOR(B) reg1, reg2 Exclusive OR P, Z 0b0011...

  • AscetiCore ⋅ Monadic indirect variable-sized
  • Hacker page     by Jock Tanner
  • Instructions for working with status register. Opcode Mnemonic Description Flags 0b010100 LDSR(B) memLD(B) SR, mem Load SR from mem P, N, Z, V, C 0b010101 ORSR(B) memOR(B) SR, mem Set flags selected by mem P, N, Z, V, C 0b010110 BRSR(B) memBRS(B) SR,...

  • AscetiCore ⋅ Monadic direct variable-sized
  • Hacker page     by Jock Tanner
  • arithmetical instructions with constants and carry flag Opcode Mnemonic Description Flags 0b000000 ADC(B) reg reg ← reg + C P, N, Z, V, C 0b000001 INC(B) regADD(B) reg, 1 reg ← reg + 1 P, N, Z, V, C 0b000010 ADD(B) reg, 2 reg ← reg + 2 P, N, Z, V, C...
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