The mezzanine, your gateway to off board IO

Going over the memory map from the REV3 board, the astute will notice the entire IO range selects the AVR request grant logic. This poses an issue for off board requests from the mezzanine connection. To resolve this, the XSIN (transceiver inhibit) signal is utilized. XSIN is a active high signal (for now) that cuts off the bus transceiver output enable pin. This in effect leaves the bus available to the mezzanine connection:

When the loop starts inside the firmware the AVR (an ATMEGA32E micro controller)  is just poling for IO requests. When it catches one, the MRDY state is already asserted on the CPU and the buses and the E and Q pulses stop in the state that they were in. This includes the data bus, r//w line and the address bus (along with all the other control signals as well). Immediately following this, it reads the XSIN line and determines if it is high. If so the IOGNT_ signal is immediately sent to the request/grant circuit and the read / write cycle can continue. This does have the disadvantage of added delay and a momentary clock stretch on every IO request, however it is very short, only a few cycles of the system clock. This was a needed trade of to keep the selection logic as simple as possible without expanding to a higher chip count.

In order to use the mezzanine expansion connector, the IO request logic must be replicated on the expansion. The IO request must also be assigned to an unused address in the IO range (for example, any address in A010-AFFF). The selection signal must be active high and linked to the XSIN line, which means that a standard address decoder must either have active high outputs or be inverted before using the signal. The XSIN pin is an input on the AVR, and it is pulled low by a 10k resistor. Only one output on the expansion should select this pin, because the logic on this line is push pull and multiple signals driving the pin high could cause a short circuit. During reset the AVR pulls this line high to zero the bank register. Currently I can not test the mezzanine until I resolve the potential short circuit. This is likely to change to simply having the reset pin for the register driven by RES (inverted RES_, which is generated by the reset circuit) but it was not high on the list of things to work out in this board revision, and so it was omitted. I am also considering changing the functionality of the pin XSIN to active low, by building out logic. Since the actual scope of the signal is for only one device it makes better sense to not make this a priority over other things which could potentially take more board space. The advantage to this is all of the signals going into XSIN could be open collector outputs and this would drastically increase the usefulness of the signal in a multi-slot expansion set up, if for instance somebody were to build a breakout with multiple slots.

If you'd like to learn more about the HB63C09M follow this link to the main project page.