kcp53001-block-diagram.jpg

This block diagram illustrates my vision of a Furcula-to-Wishbone bus bridge. The KCP53000 CPU exposes a Furcula bus for both its instruction and data ports. Once these buses are arbitrated to a single interconnect, the KCP53001 is used to talk to Wishbone peripherals and memory.

JPEG Image - 205.76 kB - 11/13/2016 at 15:59

Preview

block-diagram.jpg

This block diagram illustrates how the pieces of the CGIA fit together to serialize graphics data to the VGA port.

JPEG Image - 1.10 MB - 06/16/2016 at 18:57

Preview

forth-3.png

Here, I draw a GEOS-inspired dialog box-like thing, interactively as you can see.

Portable Network Graphics (PNG) - 22.93 kB - 04/11/2016 at 20:23

Preview

forth-2.png

Here, I'm writing software to draw simple boxes to the screen using the XOR operator directly on the framebuffer bitmap.

Portable Network Graphics (PNG) - 54.16 kB - 04/11/2016 at 20:22

Preview

forth-1.png

Finally got block storage working inside the emulator, and along with it, a visual block editor. It's based on my own Vi-Inspired Block Editor (VIBE).

Portable Network Graphics (PNG) - 52.55 kB - 04/11/2016 at 20:21

Preview

kes-eforth-rectangles.png

I tried to get a nice, more or less pretty, static demo for a screenshot on Twitter. But, bugs happened, and I ended up having to debug. Turns out, it made for a better screenshot, because it shows a more realistic user experience. Funny how that works!

Portable Network Graphics (PNG) - 15.10 kB - 04/09/2016 at 14:13

Preview

kes-eforth-coldboot.png

When you first "power-on" a Kestrel-3 emulator, it can drop you into the Forth programming language environment. (The Kestrel-3 emulator aims to emulate the Digilent Nexys-2 board, and so has 16MB of RAM.)

Portable Network Graphics (PNG) - 6.09 kB - 04/09/2016 at 14:12

Preview

20160322_231722.jpg

Schematic, recalled from memory, of the computing elements of the Kestrel-1 home-made computer. What is NOT shown is the DMA circuitry to load code into RAM under host PC control, and reset logic.

The schematic has one error in it: the BE line is tied high through a 1K resistor, just like the RDY line. This lets the IPL circuitry tri-state the CPU's address and data buses under host PC control.

JPEG Image - 4.24 MB - 03/23/2016 at 15:39

Preview