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Kestrel Computer Project

The Kestrel project is all about freedom of computing and the freedom of learning using a completely open hardware and software design.

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With each passing day, technically capable consumers of computing technology increasingly lose their rights with computer hardware. While some look to prominent Linux suppliers as an escape from the Intel/Microsoft/Hollywood oligarchy, I have taken a different route -- I decided to build my own computer completely from scratch. My computer architecture is fully open; anyone can review the source, learn from, and hack it to suit their needs.

From the main project website:

  • No back doors. No hardware locks or encryption. Open hardware means you can completely understand the hardware.
  • No memberships in expensive special interest groups or trade organizations required to contribute peripherals.
  • No fear of bricking your computer trying to install the OS of your choice. Bootstrap process is fully disclosed.
  • Designed to empower and encourage the owner to learn about and even tweak the software and the hardware for their own benefit.
  • Built on 64-bit RISC-V-compatible processor technology.

More precisely, the Kestrel-3, my third generation design, aims to be a computer just about on par with an Atari ST or Amiga 1200 computer in terms of overall performance and capability, but comparable to a Commodore 64 in terms of getting things to work.

kcp53001-block-diagram.jpg

This block diagram illustrates my vision of a Furcula-to-Wishbone bus bridge. The KCP53000 CPU exposes a Furcula bus for both its instruction and data ports. Once these buses are arbitrated to a single interconnect, the KCP53001 is used to talk to Wishbone peripherals and memory.

JPEG Image - 205.76 kB - 11/13/2016 at 15:59

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block-diagram.jpg

This block diagram illustrates how the pieces of the CGIA fit together to serialize graphics data to the VGA port.

JPEG Image - 1.10 MB - 06/16/2016 at 18:57

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forth-3.png

Here, I draw a GEOS-inspired dialog box-like thing, interactively as you can see.

Portable Network Graphics (PNG) - 22.93 kB - 04/11/2016 at 20:23

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forth-2.png

Here, I'm writing software to draw simple boxes to the screen using the XOR operator directly on the framebuffer bitmap.

Portable Network Graphics (PNG) - 54.16 kB - 04/11/2016 at 20:22

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forth-1.png

Finally got block storage working inside the emulator, and along with it, a visual block editor. It's based on my own Vi-Inspired Block Editor (VIBE).

Portable Network Graphics (PNG) - 52.55 kB - 04/11/2016 at 20:21

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  • New VDC-II Core Might Replace CGIA Concept

    Samuel A. Falvo II03/26/2020 at 17:34 0 comments

    Followers know that I've pivoted this project several times.  And I'm sure I'll pivot several times more in the future before I am satisfied with the outcome.  This post is to announce my most recent pivot.

    To help factor the project down into more manageable chunks, I've been convinced by others (and I agreed) to target the RC2014 backplane standard; specifically the RC80 variation, with a CPU card and one or more supporting I/O cards.  However, I need to get my feet wet with designing FPGA logic that couples with a 7.3728MHz, 5V bus that speaks the Z80 protocol first.  Therefore, before I decided to not start with the CPU card, but rather, with some manner of I/O card.  I already completed the MGIA core for the Kestrel-2 family, so I figured this would be a good option to get working first.

    There are some problems that I needed to resolve first though, like how to access video memory and so forth.  The TMS9918A uses an indirect approach for this, but so does another chip which seemed closer to my immediate needs: the Commodore CSG 8563 and 8568 VDC chips.  As I was studying the Commodore 128 Programmer's Reference Guide, I noticed this chip has a fair bit of similarity with what I'd originally hoped to see in the CGIA core as well.  Not only that; but, the HBIOS software on my RC2014 has a CSG 8563 driver in its source tree already, so a motivated developer can have a much easier time porting the system software.  Creating a VDC variant seemed to be the logical choice.

    So, I've decided to make a small diversion and focus my development efforts on building a project with a reasonable successor to this chip, which I've dubbed the VDC-II core.  To minimize costs and as many risks as I can, I've decided to build the prototype of the core in a TinyFPGA BX module.  Although far more resource limited than the icoBoard Gamma, it does at least have 16KB of block RAM inside it, which is enough for an 80-column text display with 16 colors, or a 640x200 monochrome bitmapped display, which is a good match for what the Kestrel-2's MGIA core can already do, and what CP/M software reasonably expects.  I suspect I'll be able to reuse much of what I'd already written for the MGIA.

    I want to see the VDC-II core to completion; if nothing else, once the basic core is working, I think I can expand upon it in ways similar to how the V9958 expands upon the TMS9918A.  If so, then perhaps the VDC-II and its successors can become the new video core for the Kestrel-3 (see?  I told you I was making progress on the Kestrel-3!).  I can also see this project as being something which I could perhaps sell one day on Tindie, CrowdSupply, or some similar outlet as an RC2014 board kit.

    So, with that in mind, I think I'm going to document this project separately from the Kestrel-3 project.  Yes, it'll most likely end up as the Kestrel-3's video core; but it has wider applicability if I can drive it to completion.  I know my track record here isn't stellar.  But, I'm willing to at least try.  I see this challenge as practice for more ambitious goals in the future.




  • Still not dead, I promise.

    Samuel A. Falvo II03/26/2020 at 17:19 0 comments

    So, it has been quite a while since I made any progress updates on this project.  At least, on Hackaday.io (I'm vastly more active on Mastodon).  Surprisingly, though, the project is not dead.  Progress is slow, yes.  But, you've always known that.

    Since acquiring my current day-job, work has drained me of both time and initiative.  I am, however, and perhaps nonetheless, progressing.  I just haven't always had the process down to where I post every time progress is made.

    I have sort of pivoted the project somewhat.  My long-term goals remain the same as they always have: a single-board computer with a RISC-V processor and custom video core, some reasonable means of expansion, and so forth.  How to achieve those goals, however, has so far diverged from my last recorded plan.  (If you can call it a plan.)  In fact, my current tack appears to qualify more as a "plan" than any prior approach I've taken so far.

    To keep the topic of these posts poignant, I'll stop here, and post my current plans in a follow-up post.  For now, though, just be aware that Kestrel-3 isn't dead.  I'm still here, and I'm still hacking.  :)

  • Interest in KCP53000-based Solutions

    Samuel A. Falvo II05/28/2019 at 15:28 0 comments

    I now have another group interested in the evolution of the Kestrel Computer Project.  In particular, I collaborate on the design and construction of various fursuit/cosplay ideas, and my Kestrel project has come to light there.  We have been having some issues with the Teensie board we've been using in the past (not enough I/Os), and with Raspberry Pis (too slow I/O; the AXI -> AHB/APB bridge is just too costly to keep up sometimes; also, not enough I/Os), and so now they're interested in the possibility of using FPGAs programmed with a KCP53000 or KCP53000B processor for their embedded development needs.

    Cool!

  • Progress on KCP53000B, IFU

    Samuel A. Falvo II05/28/2019 at 15:26 0 comments

    I think I've completed the (Tilelink) IFU design.  I emphasize "think", because without the rest of the processor being built, it's not yet possible to know if I'm truly done or not. My next major step is to work on the IXU design.  But, before that works, I would like to make an intermediate design which couples the IFU with the ROMA core (thus letting me read from flash ROM) and passing the lower 8-bits of each "instruction" fetched out to a set of LEDs.  This will provide visual confirmation that everything is working.

    I'm kind of wondering if creating a Wishbone B4 pipelined IFU has value as well.

  • CPU Update: CSRU Completed

    Samuel A. Falvo II04/09/2019 at 05:58 1 comment

    I'm happy to report that I've completed the CSR Unit, or CSRU for short.  This is the block of logic which implements all of the CSRs (Configuration and Status Register) mandated by the RISC-V Privilege Spec 1.10 as of this posting.

    It's my first real implementation of logic using nmigen as a hardware development tool.  And, I must say, I'm really quite impressed with it.

    The CSRU takes up 1157 of the 7680 logic cells of the iCE40HX8K FPGA.  This might well be entirely too big for the finished design, however.  If I remove all of the performance counters, some of the useless read-only registers like MARCHID and MVENDORID, etc., I can drop the resource consumption down to 769 LCs.  And, I can reduce this still further by ignoring the priv-spec requirement for WLRL fields (treating them instead as WARL fields, as the original KCP53000 does), which will let me throw away 59 of the DFFs used to build out the MCAUSE register, just to name one example.

    Also, with the CSRU as-is, the fastest clock speed is just a smidge above 50MHz.  This isn't very much, unfortunately; once the rest of the processor is implemented, I predict the completed processor circuit will need to be clocked somewhere in the 16MHz to 25MHz range.  Of course, reducing the CSRU complexity will help drive maximum clock speeds higher, but not by much (52MHz in the above example reduction); and, it'll come at the cost of no longer being compatible with the RISC-V priv-spec.

    For now, I'm going to stay the course with the 1157 LC design, knowing that it's just a few small tweaks to the source code to enable or disable certain features.  Using a higher-level HDL representation like nmigen is a big confidence booster for experimenting with different design configurations later on.

    Next Steps

    According to my personal project plan, my next step is to work on the Integer Execution Unit, or IXU.  This is the state machine logic that handles actual instruction execution.  It'll accept instructions from an instruction queue (IQ), rather than fetch them directly.  It'll also be responsible for helping to detect and act upon interrupts and synchronous trap conditions as well.

  • KCP53000B Processor Specs Drafted

    Samuel A. Falvo II03/16/2019 at 03:14 1 comment

    Per the last project log, I will be working on a revision of the KCP53000 suitable for proving the Kestrel-3 design.  As with all things on this scale of complexity, I'm starting out by drafting a crude set of specifications that'll help guide the development.  You can find the specs here: http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/d0c100b35693b93b

  • Serial Interface Adapter Now Hardware Proven

    Samuel A. Falvo II11/26/2018 at 18:33 0 comments

    I'm happy to announce that the Kestrel-3's Serial Interface Adapter (SIA) core is now hardware proven and works reliably.  This is a major stepping stone towards the evolution of the Kestrel-3 design.  The complete test circuit comes to about 495-ish look-up tables, which is surprisingly large for how limited the SIA is; however, it's at least not gigantic either.

    My current roadmap from this point forward is as follows:

    Port the KCP53000 away from Furcula/Wishbone and retrofit it to use a TileLink 1.7-compatible bus interface.  This will allow me to build a simple echo server so that I can fully test the SIA core, perhaps even interactively.  (I won't have any RAM to work with at this point, as the RAMA core has not yet been designed.)

    Only after the 53000 processor has been ported to run on the Kestrel-3 will I start work on the RAMA core.

    Once both the 53000 and the RAMA core are implemented, I can then try to port the Kestrel-3 port of DX-Forth onto the platform.  This will also involve somehow using a second SIA core for a prototype mass storage interface as well; not having the ability to load and save blocks of source code would be a severe inconvenience.  Regrettably, at this point, nothing will be DMA-driven.  But, interrupts will be supported, so there's that.

    Finally, after all that is done, I can start to design the next-generation processor, the 53010.

  • Big Trouble with Little Verilator

    Samuel A. Falvo II10/31/2018 at 16:39 0 comments

    I'm currently encountering significant difficulties using Verilator to write some integration tests for the Kestrel's SIA (Serial Interface Adapter) core.  Formal verification says everything should work, but Verilator is giving completely different results.

    Some external help from ZipCPU suggests that the problem lies in the specific subset of Verilog I'm using to write my core's logic, so I'll be looking to retrofit the cores as time permits.  Unlikely to be this week or next, though, due to holidays.  Hopefully, I can get some time in to fix this before December though, as I'll be busy with a whole new set of holidays!

  • On TRIPOS vs. BOAR Project

    Samuel A. Falvo II10/28/2018 at 03:59 0 comments

    The relatively recent and on-going legal actions between Cloanto and Hyperion Entertainment has me concerned about implementing VertigOS as a port of the BOAR Project.  The BOAR Project is a clean-room implementation of a proper subset of AmigaOS. including only the exec.library and dos.library components of the operating system.  While not binary compatible with AmigaOS, it should be source compatible with a large number of native AmigaDOS console applications, particularly those which treat BPTRs as opaque references.  (BOAR implements all DOS pointers as APTRs instead of BPTRs.) BOAR's library and device driver APIs are sufficiently powerful to enable a significant reproduction of actual AmigaOS libraries (albeit disk-resident) that, frankly, has me concerned that I might become a future target for litigation.

    Read the full article here.

  • Symbiyosys, Formal Verification, and ROMA Core

    Samuel A. Falvo II08/31/2018 at 20:57 0 comments

    Since the progress of the project is so early, I decided now is a good time to start to learn how to develop cores using formal verification.  I've so far "proven" my ROMA core's slave TileLink port to my satisfaction, and I'm going to move on to working with the SIA.

    I have implemented the baud rate generator logic using formal verification.  So far I'm pleased with the results, but I have to admit, I still have a lot to learn.  Will try to keep you folks updated with my progress.


    I'm pleased to say that the ROMA core is now operational enough to meet my needs.  This is not to suggest that it implements the complete and total TileLink interface.  On the contrary, it does not.  If you send a PUT or PUT_PARTIAL request to the ROMA core, you'll deadlock, because it just doesn't know what to do with those yet.  (It will eventually, just not at the moment.)  However, if you send it a GET request, you'll get back a 64-bit word containing what you're looking for after about 97 clock cycles.  Remember that the ROM it's attaching to is a serial flash ROM, accessed one bit at a time.

    So, progress!!


    As indicated above, the next steps are to implement the transmit-side of the first SIA core.

    I do have a SIA core implemented from last year (which is both TX and RX capable), but I'll be starting from scratch and incrementally copying the design over.  This way, I can work towards a formally-verified design from the ground up.  The alternative, taking an existing design and adding FV properties to it, takes much, much longer to complete because all the moving parts conspire to falsify your assertions in unforeseen ways.  So, by the time I'm done, the finished SIA design will inherit almost everything from last year's prototype design.  The register layout will be different, however.

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Discussions

DBJ314 wrote 03/19/2020 at 00:37 point

Hello,

Hackaday's blog recently posted an interesting article.

https://hackaday.com/2020/01/24/new-part-day-led-driver-is-fpga-dev-board-in-disguise/

It looks like a cheap fpga board with Gigabit Ethernet, and lots of io ports. Would it be an interesting target for Kestrel-3? It only has SDRAM on it; is that still a problem for you?

I love your work

  Are you sure? yes | no

f4hdk wrote 09/20/2017 at 21:09 point

Hello, 

I'm happy to see that you still continue with this project.

Have you seen my A2Z project here?

https://hackaday.io/project/18206-a2z-computer

It is quite a similar project, a full computer based on FPGA, but it is much simpler than yours. I've also coded a homemade compiler.

  Are you sure? yes | no

Samuel A. Falvo II wrote 09/22/2017 at 16:56 point

I believe I've seen it when I first joined the Hackaday community; however, I regret that I haven't been following up on my interests.  Now that I'm fully employed, I tend to focus my free time on my family engagements and, only occasionally, on Kestrel stuff.  :)  Apologies.

You are much further along in your project than I am with mine, though.  Right now, my biggest difficulty is getting reliable SD card operation.  After that, I'll need to make some kind of bootstrap mechanism.  I'm hoping progress will be more forthcoming once I achieve those milestones.

  Are you sure? yes | no

f4hdk wrote 03/25/2018 at 06:36 point

I've seen your SVFIG presentation. Congrats for finishing the Kestrel 2DX !

But I have one question : why only 48kB of RAM? That is very small, very limiting. Why don't you use several MB of external SDRAM present on each FPGA board? With several MB, the computer would be much more useable (like A2Z : https://hackaday.io/project/18206-a2z-computer )

  Are you sure? yes | no

Samuel A. Falvo II wrote 03/25/2018 at 07:12 point

f4hdk - Thanks for the feedback.  Finishing the 2DX is a major achievement for me, and is an important stepping stone to achieving the Kestrel-3 design.

With regards to your specific question, though, I've explained this numerous times in the project logs and even in the video -- I was utterly and thoroughly unable to raise the PSRAM chip on the FPGA board.  This leaves me limited to just using the block RAM resources that are on the FPGA itself.    If *you* know how to talk to the PSRAM chip on the Nexys-2, I'd sure welcome a patch.  Because I tried, and I've failed, for about two years.

The Kestrel-3 design will target different FPGA boards with 1MB of external SRAM, a significant improvement in RAM capacity.  There is also 512KB of SRAM on the DE-1 board from Terasic.  That same board also has 64MB of SDRAM.  However, I refuse to even try to use SDRAM.  I've learned my lesson.  Avoid SDRAM like the plague.  But, again, if you have an SDRAM controller that works and is license-compatible with MPLv2 without me having to relicense the project as a whole, then I certainly will not turn away a patch to make SDRAM work.

  Are you sure? yes | no

JL9791 wrote 11/27/2016 at 01:20 point

I see you are still working with Forth :)  I came upon this by accident when researching stack CPUs http://www.strangegizmo.com/forth/ColorForth/msg01746.html
I would like to learn Forth someday, I like the simplicity of stacks (which reminds me of my Magic the Gathering days).

  Are you sure? yes | no

Samuel A. Falvo II wrote 11/27/2016 at 01:32 point

Not having to name every intermediate computation is quite liberating.  But if taken to an extreme, it can also be quite confusing.  :)  The solution is to learn to hyper-factor your code.  A single function in C could well take 16 word definitions in Forth.  Naming procedures is a nice trade-off, because it almost serves to document why your code is the way it is.  Not quite, but good enough for most purposes.  :)  Plus, it really aids in testing code to make sure things work as you expect them to.

  Are you sure? yes | no

JL9791 wrote 11/09/2016 at 01:09 point

I have been following your project for a while, particularly because you selected the RISC-V ISA to build your CPU around.  I recently came across something I had forgotten about:  the now open source Hitachi CPUs (Sega Genesis, Saturn, Dreamcast) found here http://0pf.org/j-core.html

http://j-core.org/

Did you consider those as the brain of your Kestrel?  If not, perhaps they may be a good alternative. :)

  Are you sure? yes | no

Samuel A. Falvo II wrote 11/09/2016 at 01:16 point

Nope, and I have no intentions to either.  I've invested too much into RISC-V to change now.  Switching ISAs today would literally set me back two years of effort.  Besides, performance of RISC-V CPUs are quite good in general; that my own CPU is as slow as a 68000 should not be taken as an indication that all such CPUs are that way.

In the future, I'd like to one day hack a BOOM processor into the Kestrel, which would give it a 4-way superscalar CPU.  But, for now, I just want something simple enough that people can understand.

Another reason for adopting RISC-V is that it has learned many things from both the successes and the failures of past architectures.

Thanks for the link though.  You're not the first to suggest it.  :)

  Are you sure? yes | no

JL9791 wrote 11/09/2016 at 01:18 point

Sure thing.  Yeah, I was not suggesting you scrap all your hard work, just curious.  Glad you are coming along pretty well with it now after the..uh..hiccups :)

  Are you sure? yes | no

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