SpaceMonkeyEngineering : Minimal Instruction Set Computer : MK-II

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The SpaceMonkeyEngineering MISC MK-II represents the attempt to learn from and improve upon my first homebuilt CPU, which resulted in this new design. [Original:] This CPU will be faster, more powerful and extensible than it's predecessor! I will be using wire-wrap technique to make electrical connections on each board and interconnect boards with stackable pin-headers. Read the logs below to learn about the progress!

  • Log00 - why? why not!

    0xCAFEAFFE05/12/2016 at 22:14 0 comments

    Alright, so what did I learn from the S.A.M.I.R.A. computer system and why do I want to build another one?

    1) The ALU was alright, the MK-II will introduce a marginally more powerful ALU, which will not only be able to add and subtract, but also be able to perform logic operations and a right-shift/divide-by-2 operation which is otherwise hard to implement in software.

    2) The sequencer will be faster and more efficient in each cycle.

    3) The decoder will no longer be hardwired but implemented in a UV-EPROM lookup table.

    4) The system needs a cleaner clock source and control logic.

    5) Branch logic will be improved. Branching conditions will be: Zero, Carry, NoZero, NoCarry

    6) I need more memory. Version 1 is limited to only 256 bytes (!) of main memory, this is due to the address bus being of the same bitwidth as the data bus, which simplified the design a lot. But if I ever intend to run a more serious program (which I do), 256 bytes won't get me anywhere. The MK-II will implement a 12-bit address-bus, giving me 4kB of main memory which should be quite enough, considering that I'll be compiling the assembler code by hand ;)

    6) The hardware design needs some fixing but I'll build it on perfboard again. Testing the design on breadboard might no longer be necessary because I gathered sufficient experience with digital logic and the design already works in my emulator (written in plain C). Soldering all connections did not work very well. Neither the 'traditional' way (wires go down through the holes of the breadboard and are soldered to the IC on the bottom side of the board) NOR my pseudo-wire-wrap-technique (thin wires directly soldered onto the pins of the ICs on the bottom side of the board)
    So what I plan to do now: ICs on top, pin headers parallel to them, soldered together on the bottom, but wire-wrapped on the top. This will be easy, fast and cleaner. Pin headers are not perfect for wire-wrapping but real ones are hard to get by and pin headers work fine. The whole system will be split across multiple boards, which will be connected through one 'system bus', a stackable pin header. Extensions and peripherials can simply be added by stacking them onto the system.

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mrpeterbell wrote 05/02/2020 at 12:49 point

SAMIRA is a Persian name for a girl.

  Are you sure? yes | no

Eric Hertz wrote 11/06/2016 at 22:09 point

Cool, never seen component-side wire-wrapping before. Looks great

Groovy background-image, too.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/06/2016 at 11:59 point

Log03 got duplicated :-)

Oh and if your instructions are fixed 2 bytes, it's a pain to see you spend 4 cycles fetching 2 bytes. Just increase PC by 2 and toggle the LSB ? :-)

Keep faith !

  Are you sure? yes | no

0xCAFEAFFE wrote 11/06/2016 at 13:45 point

Thank you for the hints! There is no way to increment the PC by 2 though, this machine does not have microcode, therefore the PC can not be manipulated by the ALU, in hardware it is simply a loadable binary counter! Execution speed never really was a priority, but I will consider decreasing the period of the fetch cycles!

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/06/2016 at 14:19 point

Your PC incrementer can remain physically the same, but the LSB will come from the FSM :-) (the counter's MSB will be unused)

Going from 5 to 4 steps per instruction, a simple 2-bits counter is enough, its LSB can go to the LSB of the instruction address. Or something like that.

Even simpler : having a 16-bits memory bus, or two 8 bits memory banks (odd&even), so they can be accessed at the same time. Normal data access will simply select the memory bank from the address' LSB.

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0xCAFEAFFE wrote 09/30/2017 at 13:36 point

I just read your comment again and now I understand what you meant! Nice idea, maybe I'll actually implement it, thx! :)

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