I have an idea of "NAND ASIC" in 2x2 mm when on chip itself we only have 2-input NAND gates and metal layers do interconnects between those NAND gates to implement something as NEDONAND in silicon :)

Let's count how many gates we may have - 1 gate occupies 30x57 units (lambdas) that is 10.5x20 um:

We have 2000x2000 um area where we will put pads and power rings so available area will be about 1550x1550 um. NAND gates may be arranged in the rows one after another like this:

So in 1 row we may put 147 2-input NAND gates. Then we may have a number of horizontal lines in metal layer 1 or 2 after each row for interconnect - every line will take 3 lambdas for spacing and 4 lambdas for metal itself, so it's 7 lambdas per line plus additional 3 lambdas per spacing between next row of NAND gates. Let's calculates how many gates we may put on single chip if we will have N metal lines between rows of NAND gates:

**N=3** : interconnect will take 3*7+3=24 lambdas or 8.4um so height of every row will be 28.4um and on the chip we may have 1550/28.4=54 rows or 147*54=**7938 NAND gates**

**N=5**: 5*7+3=38 lamdas or 13.3 um so 33.3 um for row, 1550/33.3=46 rows or 147*46=**6762 NAND gates**

**N=7**: 7*7+3=52 lamdas or 18.2 um, 38.2 um for row, 40 rows or 147*40=**5880 NAND gates**

**N=9**: 9*7+3=66 or 23.1 um, 43.1 um for row, 36 rows or **5292 NAND gates**

I'm still not sure how many interconnection lines will be good enough for most designs - probably I need to "synthesize" something 1st to see how it will go...

P.S. Next step - to design compact layout for ternary multiplexer/demultiplexer ( see https://hackaday.io/project/11779/log/47306-useful-outcome ) to make ternary ASIC prototype as well (half of the chip might be binary **NAND-ASIC** prototype with for example NEDONAND implemented and another half - ternary **TRI-ASIC** prototype with for example parts of TRIADOR implemented ; )

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