SpinalHDL is an alternative hardware description language designed to provide many features that are missing in VHDL and in Verilog.

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SpinalHDL is an alternative hardware description language designed to provide many features that are missing in VHDL and in Verilog.

The language is also fully interoperable with all EDA tools because at the end a VHDL or a Verilog file is generated with your design.

So, let’s move forward !

What is SpinalHDL ?

Spinal is a open source high-level hardware description language. It can be used as an alternative to VHDL or Verilog and has several advantages over those.

Also Spinal is not a HLS approch, its goal is not to push something abstract into flip-flop and gates, but by using simple elements (flip-flop, gates, if / case statments) create new abstraction level and help the designer to not rewrite always the same thing.

Note: Spinal is fully interoperable with standard VHDL/Verilog-based EDA tools (simulators and synthetizers) as the output generated by the toolchain could be VHDL or Verilog.

It also enables mixed designs where Spinal components inter-operate with VHDL or Verilog IPs.

Advantages of using SpinalHDL over VHDL / Verilog

As Spinal is based on a high-level language, it provides several advantages to improve your hardware coding:

  1. No more endless wiring - Create and connect complex buses like AXI in one single line.
  2. Evolving capabilities - Create your own buses definition and abstraction layer.
  3. Reduce code size - by a high factor, especially for wiring. This enables you to have a better overview of your code base, increase your productivity and create fewer headaches.
  4. Free and user friendly IDE - Thanks to scala world for auto-completion, error highlight, navigation shortcut and many others.
  5. Powerful and easy type conversions - Bidirectional translation between any data type and bits. Useful to load a complex data structure from a CPU interface.
  6. Loop detection - Tools check for you that there is no combinatorial loop / latch.
  7. Clock domains safety - The tools inform you that there is no user unintentional cross clock domain.
  8. Generic design - There are no restrictions to the genericity of your hardware description by using Scala constructs

Example : RgbToGray

Let’s imagine a component which convert a RGB color into a gray one, and then write it into an external memory.

io nameDirectionDescription
clearinClear all internal register
r,g,binColor inputs
wroutMemory write
addressoutMemory address, incrementing each cycle
dataoutMemory data, gray level

This example is a very simple one, SpinalHDL offer many more features. Do not hesitate to take a look into the online documentation or the online presentation.

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