A 6-bit 2-stage pipelined RISC CPU that fits on a single page

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Inspired by, and the fact that there are lots of 4-bit CPUs and lots of 8-bit CPUs, but 6-bit ones are very rare.

* Harvard architecture with 16-bit instruction width, 64 word prorgram memory.
* Two instruction formats
* 16 registers (although not all instructions can use all 16 for all purposes)
* Program counter is an addressable register (R7)
* Memory base register (R8) allows up to 1Kword of RAM
* Subroutine link register (R15) has next instruction address automatically copied into it whenever program counter is explicitly modified
* Any instruction can be made conditional
* Autoincrementing address mode for memory store operations
* Also designed an implementation of a 6-bit ALU using a pair of GAL16V8 chips

Designed in Digital (a more advanced alternative to Logis

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BigEd wrote 5 days ago point

Thanks for your entry to #One Page Computing Challenge Julian! I like the idea of an automatically updated link register.

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Yann Guidon / YGDES wrote 3 days ago point

It's a luxury you can afford when you have plenty of registers :-D

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