TD4 by itself is very primitive architecture - it can't even add it's registers together! There is only 16 bytes for program code and no RAM. Of course, it's easy to understand, but for something serious (think OS) that's absolutely not enough!
So, the plan:
- Add RAM
- Add switchable ROM banks
But, there are a few tricky moments.
First and foremost - I want to maintain backward compatibility with existing programs for TD4. It's not very hard, but gives a restriction to work with:
- I can't change existing opcodes (there are 12 out of 16 now)
This means I can only use 4 additional instructions to implement all the features I want.
Currently, those 4 instruction are distributed like this:
- LD Imm - load from RAM to register B
- ST Imm - store to RAM from register B
- SWM Imm - switch RAM (memory) bank
- SWI Imm - switch ROM (instruction) bank
RISCy, isn't it?
Also, there is an age-old workaround - it's possible to hook up additional hardware to the I/O bus and control it using IN and OUT instructions. I consider this as a way to add some interedting functionality, like external ALU or even UART (communications!).
Another moment is jumps between ROM banks. I'm still not sure about the implementation details, so I skip this for a while.