The Components of the FBus
In order to allow dynamic configurations of all the parts of the bus we need to talk to all of them. This is the Job of the Configurator which will have one UART channel to each of the bus members to upload bitstreams, make firmware updates, or check for general health of the bus participant. It has one reserved Slot on each FBus backplane. It self does not act like a master of the bus as it has no access to the actual data lines. It will communicate to the outside world using an ethernet base protocol and is explicitly only for configuration purposes and can not perform realtime critical tasks.
These are the slots where the actual functional Nodes are located. Each will usually contain an SymbiFlow-compatible FPGA and a small Microprocessor to load the bitstream for it. It taps into up to all of the 40 differential communication lines. But if it does not require that much data throughput it can just stick with one or two or just as many as are necessary.
The FBus is designed to be synchronous in order to guarantee hard realtime properties. Therefore there will be one timekeeper per backplane that contains a set of PLLs with the ability to phase adjust the clock for each Node so that all boards on the bus are perfectly in sync.
The FBus uses the physical PCI-e connector for connecting the Nodes and the Timekeeper and the Configurator with a backplane. In this first version the Lines are designated to allow differential routing on a two-layer backplane. The data part of the PCI-E connector contains 40 differential Data Lines, one differential clock line, a TX/RX UART channel, a 5V Supply, a system voltage supply (can be anything from 5V to 24V). In the supply part of the PCI-e connector are 16 general purpose lines intended for supply of analog power supplies. All lines except the Clock and the UART are shared between all nodes.
The Configurator is compatible with a regular FBus connector, except it does not take a Clock input and the outputs are not differential but UART lines that connect to each of the FBus Nodes and the Timekeeper.
The Timekeeper has its own specification. To get better signal integrity the differential pairs are ordered different but it also has a UART chanel to the Configurator.
The Configurator is kept compatible with a Node module with different programming. Therefore, the first iteration of both of them were designed in one go. They are based on the Lattice ECP5-12F and they contain a SAMD10 for loading the FPGA bitstream, a 512 Mbit DDR2 Ram and a 32 Signal Connector to connect what ever comes to you mind.
The first version of the Timekeeper is based on two Lattice CLK5410D to provide 20 differential Clock signals.