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FBus: Open FPGA Realtime Bus

Defining and implementing a bus protocol that is built around low-cost FPGAs to enable modular and affordable control and DAQ systems.

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Data Acquisition Systems (DAQs) are either notoriously expensive or not very capable even though the operations they perform are rather basic. These systems will usually run on specialized proprietary bus protocols and most of them are optimized to operate in a master / slave logic where one board acts as a CPU and talks to the other boards via a memory like interface.

This project is here to put an end to all of that.

The FBus will be based around FPGAs which will be used rather different from the traditional approach. Usually FPGAs serve as kind of upgradable ASICs, i.e. their bitstream usually stays static in between firmware versions. Building the bus around the awesome SymbiFlow toolchain (https://symbiflow.github.io/) will allow reconfiguration tailored to the specific mode of control or measurement.

The Components of the FBus

The Configurator

In order to allow dynamic configurations of all the parts of the bus we need to talk to all of them. This is the Job of the Configurator which will have one UART channel to each of the bus members to upload bitstreams, make firmware updates, or check for general health of the bus participant. It has one reserved Slot on each FBus backplane. It self does not act like a master of the bus as it has no access to the actual data lines. It will communicate to the outside world using an ethernet base protocol and is explicitly only for configuration purposes and can not perform realtime critical tasks.

The Bus

These are the slots where the actual functional Nodes are located. Each will usually contain an SymbiFlow-compatible FPGA and a small Microprocessor to load the bitstream for it. It taps into up to all of the 40 differential communication lines. But if it does not require that much data throughput it can just stick with one or two or just as many as are necessary.

The Timekeeper

The FBus is designed to be synchronous in order to guarantee hard realtime properties. Therefore there will be one timekeeper per backplane that contains a set of PLLs with the ability to phase adjust the clock for each Node so that all boards on the bus are perfectly in sync.

Specification

The FBus uses the physical PCI-e connector for connecting the Nodes and the Timekeeper and the Configurator with a backplane. In this first version the Lines are designated to allow differential routing on a two-layer backplane. The data part of the PCI-E connector contains 40 differential Data Lines, one differential clock line, a TX/RX UART channel, a 5V Supply, a system voltage supply (can be anything from 5V to 24V). In the supply part of the PCI-e connector are 16 general purpose lines intended for supply of analog power supplies. All lines except the Clock and the UART are shared between all nodes.

The Configurator is compatible with a regular FBus connector, except it does not take a Clock input and the outputs are not differential but UART lines that connect to each of the FBus Nodes and the Timekeeper.

The Timekeeper has its own specification. To get better signal integrity the differential pairs are ordered different but it also has a UART chanel to the Configurator.

Implementation

The Configurator is kept compatible with a Node module with different programming. Therefore, the first iteration of both of them were designed in one go. They are based on the Lattice ECP5-12F and they contain a SAMD10 for loading the FPGA bitstream, a 512 Mbit DDR2 Ram and a 32 Signal Connector to connect what ever comes to you mind.

The first version of the Timekeeper is based on two Lattice CLK5410D to provide 20 differential Clock signals.

  • 1 × ECP5-12K SymbiFlow compatible FPGA on a bargain with a lot of IO
  • 1 × SAMD10D13 leightweight ARM

  • Second Board Soldered & a Manual Stencil Holder

    flowa day ago 0 comments

    Unfortunately I forgot to select the option to get the solder stencil cut to size. So It was quite uncomfortable to work with. And on the first Board it often slightly warped away from the Board an caused solder paste leaking around the pads. I tried my best to hold the stencil down with my hands but one corner would always eventually lift. To combat that I laser cut a small U-shape from Plywood to have a more easy way to hold the stencil down. With that I experienced no more leaking solder pads.

    Probably I was just reinventing the wheel. Nevertheless, with this thing I managed to solder the second board and it turned out perfect except for two little tombstoned 0402. And there it is:

  • A Target: an Inverted Pendulum

    flow3 days ago 0 comments

    Working on electronics only gets a little bit dry so I decided to make a small example project using the actual FBus system. I settled for the most popular example to apply control theory: the inverted pendulum. The first parts for it already arrived :-).

  • First Board soldered

    flow04/08/2019 at 22:34 0 comments


    The first Board is soldered :-). On this board I did not populate the DDR2 memory or the associated power supply to reduce the total points of possible failure.

    As a first test I flashed a bootloader on the SAMD10 and it worked :-). In the next days I will implement bitstream loading for the Lattice ECP5.

  • Waiting for the stencil...

    flow04/06/2019 at 10:53 0 comments

    Currently, I am waiting for the stencils and the solder paste. I made an adapter to connect the power supply and the programming UART to the boards. I allready broke the pins of one PCI-e connector, turns out they are quite fragile. Therefore, I decided to also make a small laser cut enclosure to add some rigidity.

    To test the basic operation I clumsily soldered on the SAMD10D13, a flash, and the 3.3V power supply. I was able to flash a small "hello world"... and it blinks :-)

    Looking forward to get the FPGA board working!

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