Yetanother simple CPU of TTL chips.
Progress is getting easier. I now have the XFR register working, and verified that indirect addressing works. YEAH! There was a debugging session - now that I needed to load the RAM with data, I discovered that the data was not loaded in the correct address. Finally (with a help of a Saleae logic analyzer) I had that Doh! moment - the monostable generating the LD1/2 pulses (you can see the capacitors on the picture) was wired wrong and fired LD1 and 2 at the same time, instead of after each other. Now the manual load works as advertised
Then there was a challenge with the PC jumping ahead 3 adresses when going from 7 to 8 - it turned out the LoadCounter line was floating (the LDP signal is not hooked up yet). It proves again that ALL inputlines to a chip must be tied High/Low if they do not have a signal. Of course I knew that, I was just being lazy/forgetfull/optimistic.
Hooking up the A and B registers was trivial, and the readout is temporary, just to convince myself that I load them with the indirected content.
Next is placing the ALU, where A/B display is. I'll use the '283 simple adder, and inverters to make it a subtraction - 2 chips (4 for 8bit wide. Note the room reserved for extending SEL and PC when going from 4 to 8bit). The LEQ detection is challenging me trying to minimize chipcount to do it.
It is getting tight on breadboard space. (I have more of them, but I'd rather not) Planning to move the INP and (not yet constructed) OUT unit to the left. That places all human I/O on the left, and right is Internal, I thus will use the "bus" (the strip board i the middle), and it is planned to have LEDs on it, too, so that removes one of LED bars. I had sort of semi-planned not to use "bus" in SUBLEQ ("only" ENR and INP (and RAMdata) are tristate) but that's the fun or point of doing a project like this - challenging the loosly laid plans to deliver in RealLife.
The Microsequencer is causing gnashing of teeth. ( I've updated the diagram/tables in previous log wit the corrected correction fix, revised. )
But now most signals work - ie they match my intended flow from the post "Block diagram". Time will tell if that works.
Still missing is LDO and LDP signals, but they're easy.
Actually I only wanted to test the Manual Load circuit, where two monostabes trigger the Input latch and a write to the RAM. They would need to go through some sort of "OR" operation wit the signals from the MicSeq which would generate the same signals under some conditions.
Originally I thought the MicSeq would be dead easy, as I had one (negative) logic line for each step, and a simple OR or AND would be enough for where a condition is needed. Like, "Increment PC on step 2 and 4 and on 6 if LEQ is false". But, the 74LS138 has a negative signal, and most registers trigger on an edge and need delaying until the RAM output has stabilised (ie can not trigger on the same edge). That is handled by AND-ing in the clock, so I get two edges on one step.
Note: Where it says "Seq" in the table it that step, ie Sequence5 in the ENR(EnableResult) column. I've tried to factor where I can but it still ends up with 26 gates on 7 chips (using triple-input gates doesn't help the chip count) ! And this is not even a proper instruction decoder, as there is only ONE instruction. Sigh. Defenitly will be using a EPROM in the future, but for now I wire this up. Suddenly I get worried I will rewire countless times as I discover errors, so I start using LogiSim and yes ... errors. The above is the corrected version, and below the circuit. (yeah, I could format it prettier, but that's not the point here)
If you trace backwards you can see that DOD (RAM DataOutputDisable) is simple, only one OR and NOT gate, but that the LXP (Load the indirect address register) is 5 gates.
I'll think I start with the Program Counter. It is a counter. I happen to have a lot of 74LS197 (salvage from a surplus store) so I use one (or two) of them.
4 bit counter. I use the Arduino tester, to verify that I truly understand the chip. It actually is two counters; one single bit, and one with 3 bits. There is NO CARRY. OK, as the count clock is negative-edge sensitive it simply means putting the highest digit of the previous stage into the clock of the next counter.
The Clear will go to the global Reset line.
It will be another 74LS197 counter driven by the clock going into the 3->8 decoder 74LS138, where one of the 8 lines is
high low for each tick. Route to each latch/tristate, with inverters, as appropiate. I hope that the "random logic" to get things happen at the correct clock edge will remain reasonably simple.
The microsequencer works as advertised, ie one of each of the 8 controllines go low at the desired step. (The rest is not on the above picture:) The PC gets the INC on step 2 and 4, and conditionally on step 6. Currently 4 ddressbits cycle correctly, address the RAM, and data can be stored and retrieved (for now by manually setting datalines and manually toggling WriteEnable). It is a 4bit machine for this phase, and the LED bar shows address and data.
The button debounce is giving me headaches - I cant get 100% releiable single step, and I do not know if reason is the button is too bad, the breadboard gives way/glitches, or I have stray signal pickup. (The latter seems likely - I sometimes get a "step" when touching some wire). It will do for the while being.
(Some while later): Clock works. The PC increments as it should at right microstep, including a manual simulated LEQ branch (ie do not increment, but the jump isnt there yet). Also the RAM access works. A manual (moving jumpers) load of data shows that read and write work.
The green display is temporarily both 4 bit address and 4 bit data. (Everything is 4 bit for the while being)
I think I now have the right block diagram. The first one was easy, took 5 minute sketch, the SUBLEQ is sooo easy. Yeah - after thinking about it, there was an error here. Oh and an ommision here. And hey, indirect addressing on everything! "Rinse and Repeat" the design a few cycles.
Note that input and output is included as an extension to the pure SUBLEQ. There is no other instruction than SUBLEQ, so INP and OUT are memorymapped, ie addressing location 0 will read INP (switches) or write OUT (7seg digit). Edit: It is not strictly memory mapped, as referencing address zero changes the way the instruction executes, rather than redirect the address.
XFR, Areg and Breg are latch-registers, PC is a presettable counter, SEL a 2-to-1 selector, SUB does subtraction and signals LEQ. The ZER senses address zero. ENI/ENR are tri-state gates (can't seem to design my way out of using tri-state on the databus, as it is bidrectional).
This of course needs some squencer to control, the microsequencer
The last line is the Hardwired Loader - to be implemented as a push button that transfers INP to RAM, then increments PC.
It started about 3 years ago with viewing the Ben Eater series on building a simple CPU with just breadboards and TTL. Although the 74's are "relativly cheap", there are lots of them, and the total expenditure kept me back. Ben Eater sells the kit, but that makes it a boring repeat. In autumn 2019 I bought a selection of chips, both to cover that project, and a "suitable" selection of others, and a few to spare.
I want to experiment with the challenges of of doing my own. I know the architecture of CPUs as such, so this is purely fun, as a puzzle. I want to extend the BenEater design with more RAM, an IO subsystem (keypad input, Serial?), something to load RAM, Interrupt handling, and paging. Of course at that point it isn't a "simple CPU" anymore.
As the title picture shows, I have constructed a tray so I can easily take it out to play, and put it back even in mid work. On a wooden base I have a large conductivefoam area to store chips, there is a 5V supply, and an Arduino to act as a test generator, and bulk storage IO device. Breadboards obviously, and a strip-board bus in the middle (rather than using even more breadboard)
"Walk before you run" - so this first project on my CPU constructor kit simplifies CPU capabilities even further: One instruction, avoid "bus"/Tristate, start with 4bit (address and data).