Close to summer break, where brains stop to function and the incentives tend to be ice cream rather than a successfully blinking but heat producing FPGA board. It's time to summarize what works and what doesn't, plus a small road map:
- Designs that stick to certain design rules (undocumented, but covered by a number of test cases under `test/conversion/toYosys`)
- Integrating external Verilog/VHDL implementations (VHDL support yet subject to volatilities)
- A few ECP5 primitives (blackbox wrappers)
- Simple `$mem` block inference
- Functional simulation models for most of the ECP5 blackbox primitives
- Automated DSP element inference (must be explicit)
- Support for negative and dual edge events inference and several I/O standards
- Support for sequential programming (@instance style)
- Coverage for some corner cases with variable usage (some tests
for it are marked to fail in the test suite)
- Support for the fully fledged multi port memory inference (this is is also a yosys issue being worked on)
- Handling of yosys exceptions: these terminate the python interpreter without error shown in the Notebook environment.
As of now, a lot of complexity is introduced by legacy MyHDL behaviour and support of existing structures. To support inference of all kinds of constructs, the complexity would be very much increased (which is considered 'dangerous' at this time, as the underlying architecture might still receive a redesign).
To be able to create working prototypes anyhow, the current strategy tries to follow the 'blackbox' approach:
Instead of trying to make the synthesizer guess what it should create from a functional description, we pick things from a library that is known to work, then we wrap them such that they look like our functional description (that plays right in simulation). Even better, in MyHDL we can pack them into the same functional block. We just need to verify that the actual hardware implementation behaves exactly the same as the functional simulation. This functional block also provides the support for high level constructs, for example, a class object that supports multiplication and infers to the matching black box multiplier element underneath.
For example, a PLL on an ECP5 FPGA is defined as @blackbox entity `EHXPLLL`, including a simple (currently imprecise) simulation model for its up to four clock outputs, however, for synthesis, this model is ignored and the explicit (yosys specific) inferral routine is called to reserve the matching primitive for the final wiring. For another implementation method (be that a different synthesizer or different silicon architecture), another implementation is added as python sub-function decorated with the @synthesis(method) decorator.
This blackbox API is now considered 'set' and will only change marginally with respect to some argument/parameter handling. Now here comes the roadmap:
- Creating a library of working modules that infer and verify against yosys synthesis output as correct, using Co-Simulation
- Improve framework to swap easily between external blackbox V*-HDL implementations and MyHDL implementations
- Get all memory inference scenarios completed (this is important to run a RISC-V design in pure MyHDL)
- Support I/O standards up to the interface
- gensoc integration (SoC generator for register maps, bus decoders, etc.)
- Testing, testing, testing...
The full goal: Running just everything out of a python shell