..from Python Jupyter notebook to silicon

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This is a documentation project in progress to document hardware synthesis from Python and the MyHDL module.
MyHDL -- the better Verilog or VHDL -- can interface with any other Python module, so it can with yosys through the pyosys extension.
Means, it is possible to generate a synthesizeable representation of your hardware description. And, since this should be easy to reproduce for now (because in development stage), the environment is supplied as a jupyter notebook. If you're not familiar with that: It allows you to run python code from the browser. So, after all, yes, you can synthesize from the browser in a virtual machine.

Beware: It is an experimental playground, a priori designed for learning purposes.
Do not expect full functionality.

The quick start: Launch the link below to start the virtual machine inside the service

[jupyosys binder]

You can also find some up to date information here in my blog posts.

The virtual machine contains:

  • A jupyter notebook installation (obviously)
  • A recent pyosys module build (including full yosys functionality)
  • An icarus verilog installation to verify and simulate verilog code
  • The MyHDL 'jupyosys' fork supporting synthesis
  • Various utilities to display waveforms and dot graphics

What you basically can play with in this binder:

  • Run code to describe and simulate a hardware element
  • Dump a waveform trace
  • Synthesize into yosys primitives and display
  • Verify the synthesis working correctly by Co-Simulation

  • From browser to FPGA in five seconds

    Martin05/22/2020 at 08:27 0 comments

    Still far away from synthesizing just any design, but when following the design rules, things basically bake into a *.svf file that downloads to the corresponding target board.

    Last commits (inside the 'hacker space') add the mandatory blinky example for the Versa ECP5 development kit from Lattice Semi.

    Those who have been dealing with the Diamond toolchain for a while may remember some pain: The downloads to the target could take up to 30 seconds already.

    The current setup shortens the translate-synthesize-map-place'n'route iteration cycles significantly. So the newly added blinky example should download within five seconds (after installing all the necessary packages, setting permissions and running the container locally). Not that this should encourage trial&error coding, but it might stop you from having too many smoke breaks.

  • Going real

    Martin05/06/2020 at 16:21 0 comments

    Starting out as a documentation project with tiny steps and rather frequent updates, it's now moving towards:

    • Getting real world (existing) designs to spin
    • Augmenting the test benches with plenty of uncovered corner cases
    • Not breaking stuff (unit tests for Jupyter notebooks, too)

    Also, so far all has been 'virtual', i.e. running in the browser only. The next milestone is to get a complex CPU design running (still undecided which one it is going to be, but certainly one of the MaSoCist choices).

    The hard part (which needed a lot of playing and revamping) is to support a rather large number of corner cases that have to do with conditional code:

    if state == t_state.RESET: = 0xff
    elif state == t_state.RUN: = c
    else: = 0xaa

    This snippet is just supposed to assert a signal, decided upon a state condition, let aside the context for now (whether behind a flip flop or combinatorial logic)

    In the silicon, this basically creates multiplexers. And it gets very interesting, when a case is omitted (like the 'else' clause), you might remember issues with combinatorial loops.

    Hopefully with the recent release, I've gotten the corner cases right.

    Here's where the testing comes in:

    • Testing against a working reference
    • Testing that the examples are correct

    And this is where Python performs exceptional: it provides probably the most convenient ecosystem to test stuff. This is now also found in the [ Binder based virtual machine ].

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